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Related publications (28)

Negative Resistance in Cascode Transistors

Elison de Nazareth Matioli, Armin Jafari, Palliyage Srilak Nirmana Perera, Mohammad Samizadeh Nikooytabalvandani

Cascode topology which includes a high-voltage GaN and a low-voltage Si transistor is an attractive device concept, which uses the low ON-resistance of GaN while still being compatible with Si gate drivers. It demonstrates the highest threshold voltage amo ...

2020

Data Structures and Algorithms for Logic Synthesis in Advanced Technologies

Eleonora Testa

Logic synthesis is a key component of digital design and modern EDA tools; it is thus an essential instrument for the design of leading-edge chips and to push the limits of their performance. In the last decades, the electronic circuits community has evolv ...

EPFL2020

On-Chip Fully Integrated Field Emission Arrays for High-Voltage MEMS Applications

Vivek Subramanian

Vacuum-sealed fully integrated diode and triode field emission arrays based on Ti Spindt-type field emitters have been developed in a scalable, CMOS-compatible process directly on Si. Diode characterization in air demonstrates effective vacuum sealing and ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM

Alexandre Sébastien Julien Levisse

Resistive RAM (RRAM) is a promising emerging Non-Volatile Memory candidate due to its scalability and CMOS compatibility, which enables the fabrication of high density RRAM crossbar arrays in Back-End-Of-Line CMOS processes. Fast and accurate architectural ...

2019

RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM

Alexandre Sébastien Julien Levisse

2019

Polarity-Controllable Devices and Circuits for Doping-Free 2D Electronics

Giovanni Vincenzo Resta

The growth of information technology has been sustained by the miniaturization of Complementary Metal-Oxide-Semiconductor (CMOS) Field-Effect Transistors (FETs), with the number of devices per unit area constantly increasing, as exemplified by Mooreâ s la ...

EPFL2019

Fabrication and Characterisation of Epitaxial PMN-PT Nano-structures

Xiao Di

Downscaling of the minimal feature size, or the gate length has been the key for the exponential im-provement of the performance of the logic CMOS integrated circuits over the last six decades. How-ever, since about 2003, some fundamental limits in the dev ...

EPFL2019

Triboelectric‐TFT Flip‐Flop for Bistable Latching of Dielectric Elastomer Actuators

Danick Briand, Herbert Shea, Rubaiyet Iftekharul Haque, Alexis Pierre Henri Marette, Xiaobin Ji, Ronan Julien Hinchet

A high‐voltage flip‐flop combining two self‐powered soft sensors with a flexible high‐voltage thin film transistor (HVTFT) is reported, and is used to electrically latch dielectric elastomer actuators (DEAs) in zero and high‐strain states. Two touch‐actuat ...

2019

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