Concept

Modified Harvard architecture

Related publications (22)

EdgeAI-Aware Design of In-Memory Computing Architectures

Driven by the demand for real-time processing and the need to minimize latency in AI algorithms, edge computing has experienced remarkable progress. Decision-making AI applications stand out for their heavy reliance on data-centric operations, predominantl ...

EPFL2024

TiC-SAT: Tightly-coupled Systolic Accelerator for Transformers

David Atienza Alonso, Giovanni Ansaloni, Alireza Amirshahi, Joshua Alexander Harrison Klein

Transformer models have achieved impressive results in various AI scenarios, ranging from vision to natural language processing. However, their computational complexity and their vast number of parameters hinder their implementations on resource-constraine ...

2023

Preconditioning techniques for generalized Sylvester matrix equations

Yannis Dirk Voet

Sylvester matrix equations are ubiquitous in scientific computing. However, few solution techniques exist for their generalized multiterm version, as they now arise in an increasingly large number of applications. In this work, we consider algebraic parame ...

2023

MOD2IR: High-Performance Code Generation for a Biophysically Detailed Neuronal Simulation DSL

Felix Schürmann, Pramod Shivaji Kumbhar, Omar Awile, Snehal Pramod Kumbhar, Ioannis Magkanaris

Advances in computational capabilities and large volumes of experimental data have established computer simulations of brain tissue models as an important pillar in modern neuroscience. Alongside, a variety of domain specific languages (DSLs) have been dev ...

ACM2023

2022 roadmap on neuromorphic computing and engineering

Srikanth Ramaswamy, Carlo Ricciardi, Elisa Donati, Yihwa Kim, Silvia Tolu, Xuan Li, Abu Sebastian, Emre Neftci, Roberto Galeazzi

Modern computation based on von Neumann architecture is now a mature cutting-edge science. In the von Neumann architecture, processing and memory units are implemented as separate blocks interchanging data intensively and continuously. This data transfer i ...

IOP Publishing Ltd2022

In-Memory Hardware and Architectural Extensions for Workloads Acceleration

William Andrew Simon

Utilization of edge devices has exploded in the last decade, with such use cases as wearable devices, autonomous driving, and smart homes. As their ubiquity grows, so do expectations of their capabilities. Simultaneously, their formfactor and use cases lim ...

EPFL2022

Exploring negative capacitance and neuromorphic devices based on CMOS-compatible ferroelectric HfO2

Carlotta Gastaldi

Ferroelectric materials are explored for numerous applications thanks to their properties associated with electrically switchable spontaneous polarization. Perovskites are an established class of ferroelectrics used for sensors and actuators. However, they ...

EPFL2022

Real-Time Nonlinear Model Predictive Control for Fast Mechatronic Systems

Petr Listov

This thesis presents an efficient and extensible numerical software framework for real-time model-based control. We are motivated by complex and challenging mechatronic applications spanning from flight control of fixed-wing aircraft and thrust vector cont ...

EPFL2022

AstriFlash: A Flash-Based System for Online Services

Babak Falsafi, Siddharth Gupta, Lei Yan, Mark Johnathon Sutherland, Yunho Oh

Modern datacenters host datasets in DRAM to offer large-scale online services with tight tail-latency requirements. Unfortunately, as DRAM is expensive and increasingly difficult to scale, datacenter operators are forced to consider denser storage technolo ...

2023

Biosensors for Bimolecular Computing: a Review and Future Perspectives

Sandro Carrara, Danilo Demarchi, Simone Aiassa

Biomolecular computing is the field of engineering where computation, storage, communication, and coding are obtained by exploiting interactions between biomolecules, especially DNA, RNA, and enzymes. They are a promising solution in a long-term vision, br ...

SPRINGER2020

Logic-in-memory based on an atomically thin semiconductor

Aleksandra Radenovic, Andras Kis, Mukesh Kumar Tripathi, Ahmet Avsar, Yanfei Zhao, Guilherme Migliato Marega, Zhenyu Wang

The growing importance of applications based on machine learning is driving the need to develop dedicated, energy-efficient electronic hardware. Compared with von Neumann architectures, which have separate processing and storage units, brain-inspired in-me ...

2020

HetExchange: Encapsulating heterogeneous CPU-GPU parallelism in JIT compiled engines

Anastasia Ailamaki, Manolis Karpathiotakis, Raja Appuswamy, Periklis Chrysogelos

Modern server hardware is increasingly heterogeneous as hardware accelerators, such as GPUs, are used together with multicore CPUs to meet the computational demands of modern data analytics workloads. Unfortunately, query parallelization techniques used by ...

2019

Analog Control of Retainable Resistance Multistates in HfO2 Resistive-Switching Random Access Memories (ReRAMs)

Elmira Shahrabi, Yusuf Leblebici, Jury Sandrini, Carlo Ricciardi, Cecilia Giovinazzo, Oguz Tolga Celik

Resistive-switching random access memory (ReRAM) technologies are nowadays a good candidate to overcome the bottleneck of Von Neumann architectures, taking advantage of their logic-in-memory capability and the ability to mimic biological synapse behavior. ...

AMER CHEMICAL SOC2019

Engineered substrates with embedded strain relief for stretchable thin-film electronics

Alessia Romeo

Stretchable electronics are integrated circuitry that can reversibly expand and relax while retaining their functionality. This emerging technology has great potential in unconventional electronic application areas, especially in biomedical sector. To atta ...

EPFL2015

Way Stealing: A Unified Data Cache and Architecturally Visible Storage for Instruction Set Extensions

Edoardo Charbon, Paolo Ienne, Ties Jan Henderikus Kluter, Philip Brisk

Way Stealing is a simple architectural modification to a cache-based processor that increases the data bandwidth to and from application-specific instruction set extensions (ISEs), which increase performance and reduce energy consumption. Way Stealing offe ...

Institute of Electrical and Electronics Engineers2014

Virtual Ways: Low-Cost Coherence for Instruction Set Extensions with Architecturally Visible Storage

Edoardo Charbon, Paolo Ienne, Ties Jan Henderikus Kluter, Samuel Burri, Philip Brisk

Instruction set extensions (ISEs) improve the performance and energy consumption of application-specific processors. ISEs can use architecturally visible storage (AVS), localized compiler-controlled memories, to provide higher I/O bandwidth than reading da ...

Assoc Computing Machinery2014

Instruction Set Extensions for Cryptographic Hash Functions on a Microcontroller Architecture

Andreas Peter Burg, Jeremy Hugues-Felix Constantin

In this paper, we investigate the benefits of instruction set extensions (ISEs) on a 16-bit microcontroller architecture for software implementations of cryptographic hash functions, using the example of the five SHA-3 final round candidates. We identify t ...

Ieee2012

Architectural Support for Coherent Architecturally Visible Storage in Instruction Set Extensions

Ties Jan Henderikus Kluter

When it comes to performance, embedded systems share many problems with their higher-end counterparts. The growing gap between top processor frequency and memory access speed, the memory wall, is one such problem. Driven, in part, by low energy consumption ...

EPFL2010

Memory Organization and Data Layout for Instruction Set Extensions with Architecturally Visible Storage

Paolo Ienne, Yusuf Leblebici, Philip Brisk, Panagiotis Athanasopoulos

Present application specific embedded systems tend to choose instruction set extensions (ISEs) based on limitations imposed by the available data bandwidth to custom functional units (CFUs). Adoption of the optimal ISE for an application would, in many cas ...

2009

Smart camera with embedded co-processor: a postal sorting application

Marco Mattavelli, Romuald Mosqueron, Julien Dubois

This work describes an image acquisition and processing system based on a new co-processor architecture designed for CMOS sensor imaging. The platform permits to configure a wide variety of acquisition modes (random region acquisition, variable image size, ...

2008