Publications related to Fredkin gate

In-situ atomic level observation of the strain response of graphene lattice

Strain is inevitable in two-dimensional (2D) materials, regardless of whether the film is suspended or supported. However, the direct measurement of strain response at the atomic scale is challenging due to the difficulties of maintaining both flexibility ...

Nature Portfolio2023

Fully Tunable Longitudinal Spin-Photon Interactions in Si and Ge Quantum Dots

Pasquale Scarlino

Spin qubits in silicon and germanium quantum dots are promising platforms for quantum computing, but entangling spin qubits over micrometer distances remains a critical challenge. Current prototypical architectures maximize transversal interactions between ...

AMER PHYSICAL SOC2022

Further Results on Efficient Implementations of Block Cipher Linear Layers

Subhadeep Banik

At the FSE conference of ToSC 2018, Kranz et al. presented their results on shortest linear programs for the linear layers of several well known block ciphers in literature. Shortest linear programs are essentially the minimum number of 2-input xor gates r ...

2021

Three-Input Gates for Logic Synthesis

Giovanni De Micheli, Mathias Soeken, Dewmini Sudara Marakkalage, Eleonora Testa, Heinz Riener

Most logic synthesis algorithms work on graph representations of logic functions with nodes associated with arbitrary logic expressions or simple logic functions and iteratively optimize such graphs. While recent multilevel logic synthesis efforts focused ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2021

Gate Control of Spin-Layer-Locking FETs and Application to Monolayer LuIO

Nicola Marzari, Antimo Marrazzo, Thibault Daniel Pierre Sohier, Rong Zhang

A recent 2D spinFET concept proposes to switch electrostatically between two separate sublayers with strong and opposite intrinsic Rashba effects, exploiting the spin-layer-locking mechanism in centrosymmetric materials with local dipole fields. Here, we p ...

AMER CHEMICAL SOC2021

More Results on Shortest Linear Programs

Subhadeep Banik

At the FSE conference of ToSC 2018, Kranz et al. presented their results on shortest linear programs for the linear layers of several well known block ciphers in literature. Shortest linear programs are essentially the minimum number of 2-input xor gates r ...

2019

Scaling-up ESOP Synthesis for Quantum Compilation

Giovanni De Micheli, Mathias Soeken, Bruno Schmitt Antunes

Today's rapid advances in quantum computing hardware call for scalable synthesis methods to map combinational logic represented as multi-level Boolean networks (e.g., an and inverter graph, AIG) to quantum circuits. Such synthesis process must yield revers ...

IEEE2019

Fluorescence lifetime imaging with a single-photon SPAD array using long overlapping gates: an experimental and theoretical study

Edoardo Charbon, Claudio Bruschini, Andrei Ardelean, Arin Can Ülkü

Developing large arrays of single-photon avalanche diodes (SPADs) with on-chip time-correlated single-photon counting (TCSPC) capabilities continues to be a difficult task due to stringent silicon real estate constraints, high data rates and system complex ...

2019

Phasor-based widefield FLIM using a gated 512×512 single-photon SPAD imager

Claudio Bruschini, Edoardo Charbon, Ivan Michel Antolovic, Arin Can Ülkü

Single-photon avalanche diode (SPAD) imagers can perform fast time-resolved imaging in a compact form factor, by exploiting the processing capability and speed of integrated CMOS electronics. Developments in SPAD imagers have recently made them compatible ...

2019

Inverse Gating for Low Energy Block Ciphers

Francesco Regazzoni, Subhadeep Banik

In this paper we explore the technique of “inverse gating” which is a significant improvement over the ”round gating” technique introduced in HOST 2016. Round gating worked by generating timing signals to separate glitch propagation from one circuit elemen ...

2018

Exploiting Inherent Characteristic of Reversible Circuits for Faster Combinational Equivalence Checking

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù

Reversible circuits implement invertible logic functions. They are of great interest to cryptography, coding theory, interconnect design, computer graphics, quantum computing, and many other fields. As for conventional circuits, checking the combinational ...

Ieee2016

Computationally Efficient Multiple-Independent-Gate Device Model

Giovanni De Micheli, Mariagrazia Graziano, Pierre-Emmanuel Julien Marc Gaillardon, Gianluca Piccinini

Nanowire Field Effect Transistors (FETs) with multiple independent gates around a silicon channel feature ultimate gate control and are regarded as promising candidates for next generation transistors. Being inherently more complex than conventional gate-a ...

Institute of Electrical and Electronics Engineers2016

New Data Structures and Algorithms for Logic Synthesis and Verification

Luca Gaetano Amarù

The strong interaction between Electronic Design Automation (EDA) tools and Complementary Metal-Oxide Semiconductor (CMOS) technology contributed substantially to the advancement of modern digital electronics. The continuous downscaling of CMOS Field Effec ...

EPFL2015

Role of the gate in ballistic nanowire SOI MOSFETs

Christian Enz, Jean-Michel Sallese, Anurag Mangla

In this paper we report the results of Monte-Carlo simulations performed on double-gate ballistic MOSFETs with a geometry such that the gates overlap only a fraction of the channel. We present a qualitative analysis of the simulation results highlighting t ...

Elsevier2015

Biconditional BDD: A Novel Canonical BDD for Logic Synthesis targeting XOR-rich Functions

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù

We present a novel class of decision diagrams, called Biconditional Binary Decision Diagrams (BBDDs), that enable efficient logic synthesis for XOR-rich functions. BBDDs are binary decision diagrams where the Shannon’s expansion is replaced by the bicondit ...

2013

Pre-Synthesis Optimization of Arithmetic Circuits

Ajay Kumar Verma

The efficient synthesis of circuits is a well-studied problem. Due to the NP-hardness of the problem, no optimal algorithm has been presented so far. However, the heuristics presented by several researchers in the past, which are also adopted by commercial ...

EPFL2010