Publications related to Front-side bus

General and Unified Model of the Power Flow Problem in Multiterminal AC/DC Networks

This paper proposes a generic and unified model of the power flow (PF) problem for multiterminal hybrid AC/DC networks. The proposed model is an extension of the standard AC-PF. The DC network is treated as an AC one and, in addition to the Slack, PV and P ...

IEEE Institute of Electrical and Electronics Engineers2024

Beam test performance of a prototype module with Short Strip ASICs for the CMS HL-LHC tracker upgrade

Qian Wang, Simone Scarfì, Varun Sharma, Konstantin Androsov, Xin Chen, Rakesh Chawla, Tian Cheng, Werner Lustermann, Andromachi Tsirou, Andrea Rizzi, Jessica Prisciandaro, David Vannerom, Davide Di Croce, Albert Perez, Alessandro Caratelli, François Robert, Davide Ceresa, Chun Xia, Yong Yang, Ajay Kumar, Ashish Sharma, Georgios Anagnostou, Muhammad Ahmad, Francesco Fiori, Kai Yi, Jing Li, Hui Wang, Stefano Michelis, François Bianchi, David Parker

The Short Strip ASIC (SSA) is one of the four front-end chips designed for the upgrade of the CMS Outer Tracker for the High Luminosity LHC. Together with the Macro-Pixel ASIC (MPA) it will instrument modules containing a strip and a macro-pixel sensor sta ...

2022

Uncooperative Rendezvous in Space: Design of an Electronic Architecture for High Performance Avionic with Multi Sensor Input and Intensive Data Rate

Michaël Yannick Juillard

Active Debris Removal missions consist of sending a satellite in space and removing one or more debris from their current orbit. A key challenge is to obtain information about the uncooperative target. By gathering the velocity, position, and rotation of t ...

EPFL2022

Software Support for Non-Volatile Memory (NVM) Programming

David Teksen Aksun

Non-Volatile Memory (NVM) is an emerging type of memory device that provides fast, byte-addressable, and high-capacity durable storage. NVM sits on the memory bus and allows durable data structures designs similar to the in-memory equivalent ones. Expensiv ...

EPFL2021

Modeling and optimization of dedicated bus lanes space allocation in large networks with dynamic congestion

Nikolaos Geroliminis, Dimitrios Tsitsokas, Anastasios Kouvelas

Dedicated bus lanes provide a low cost and easily implementable strategy to improve transit service by minimizing congestion-related delays. Identifying the best spatial distribution of bus-only lanes in order to maximize traffic performance of an urban ne ...

2021

GPU-accelerated data management under the test of time

Anastasia Ailamaki, Syed Mohammad Aunn Raza, Periklis Chrysogelos, Angelos Christos Anadiotis, Panagiotis Sioulas

GPUs are becoming increasingly popular in large scale data center installations due to their strong, embarrassingly parallel, processing capabilities. Data management systems are riding the wave by using GPUs to accelerate query execution, mainly for analy ...

2020

Scalable Marine Bus-Tie Switch for Switchboard Interconnections

Drazen Dujic, Gabriele Ulissi

DC power distribution systems in marine applications are in the process of being established as the preferred solution for shipboard power distribution systems. This paper presents a bus-tie switch topology for the protection of such systems. The device is ...

2020

Empirical analysis of large-scale multimodal traffic with multi-sensor data

Nikolaos Geroliminis, Nan Zheng, Hui Fu

Recent advances in the network-level traffic flow modelling provide an efficient tool for analyzing traffic performance of large-scale networks. A relationship between density and flow at the network level is developed and widely studied, namely the macros ...

PERGAMON-ELSEVIER SCIENCE LTD2020

FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort

Paolo Ienne, Mikhail Asiatici, Damian Maiorano

String sorting is an important part of database and MapReduce applications; however, it has not been studied as extensively as sorting of fixed-length keys. Handling variable-length keys in hardware is challenging and it is no surprise that no string sorte ...

IEEE COMPUTER SOC2020

FPGA-Assisted Deterministic Routing for FPGAs

Mirjana Stojilovic, Dario Korolija

FPGA routing is one of the most time-consuming steps of FPGA compilation, often preventing fast edit-compile-test cycles in prototyping and development. There have been attempts to accelerate FPGA routing using algorithmic improvements, multi-core or multi ...

2019

DynaBurst: Dynamically Assemblying DRAM Bursts over a Multitude of Random Accesses

Paolo Ienne, Mikhail Asiatici

The effective bandwidth of the FPGA external memory, usually DRAM, is extremely sensitive to the access pattern. Nonblocking caches that handle thousands of outstanding misses (miss-optimized memory systems) can dynamically improve bandwidth utilization wh ...

IEEE2019

Quantitative phase imaging in biomedicine

Christian Depeursinge

Quantitative phase imaging (QPI) has emerged as a valuable method for investigating cells and tissues. QPI operates on unlabelled specimens and, as such, is complementary to established fluorescence microscopy, exhibiting lower phototoxicity and no photobl ...

Nature Publishing Group2018

Hybrid Model Predictive Control of Bus Transport Systems

Nikolaos Geroliminis, Isik Ilber Sirmatel

Schedule instability adversely affects the performance of bus transport systems. Bus bunching and similar irregularities decrease quality of bus services and increase travel times. In this regard, bus system management schemes are of high importance. Motiv ...

IEEE2018

Development and Characterisation of Silicon Photomultiplier Multichannel Arrays for the Readout of a Large Scale Scintillating Fibre Tracker

Axel Kuonen

The current LHCb detector will continue collecting data until the long shutdown 2 (2019/2020). It will be upgraded in order to operate at higher luminosity. To achieve this, two major changes are required. First the Level-0 hardware trigger limited to 1,M ...

EPFL2018

Dynamical Modeling and Predictive Control of Bus Transport Systems: A Hybrid Systems Approach

Nikolaos Geroliminis, Isik Ilber Sirmatel

Bus operations, due to their unstable nature, are inefficient when left uncontrolled with respect to retaining headways. Irregularities such as bus bunching lead to loss of time and decrease bus service quality. Development of bus transport system manageme ...

2017

Hybrid Modeling and Predictive Control of Bus Transport Systems

Nikolaos Geroliminis, Isik Ilber Sirmatel

Bus operations, due to their unstable nature, are inefficient when left to their own devices. Irregularities such as bus bunching lead to loss of time and decrease bus service quality. Development of bus transport system management schemes to avoid bus bun ...

2017

Near-Memory Address Translation

Babak Falsafi, Javier Picorel Obando, Dorde Jevdic

Memory and logic integration on the same chip is becoming increasingly cost effective, creating the opportunity to offload data-intensive functionality to processing units placed inside memory chips. The introduction of memory-side processing units (MPUs) ...

Ieee2017

ICCAD 2015 Contest in 3D Interlayer Cooling Optimized Network

David Atienza Alonso, Arvind Raj Mahankali Sridhar

Microchannel liquid cooling has been proposed since the late 2000s as a viable enabler for 3D integration of microprocessors to continue scaling of computing power in the face of increasingly reduced returns from CMOS technology scaling. Thermal and electr ...

ACM/IEEE Press2015

Two-phase flow operational maps for multi-microchannel evaporators

John Richard Thome, Navid Borhani, Sylwia Szczukiewicz

The current paper presents new operational maps for several different multi-microchannel evaporators, with and without any inlet restrictions (micro-orifices), for the two-phase flow of refrigerants R245fa, R236fa, and R1234ze(E). The test fluids flowed in ...

Elsevier2013

Power and pin efficient chip-to-chip communications with common-mode rejection and sso resilience

Mohammad Amin Shokrollahi, Harm Cronie

In bus communications methods and apparatus, a first set of physical signals representing the information to be conveyed over the bus is provided, and mapped to a codeword of a spherical code, wherein a codeword is representable as a vector of a plurality ...

2012