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Related publications (32)

High-Speed ADC Design and Optimization for Wireline Links

The ever-growing global internet traffic has increased demand for higher speed data transmission. As the bandwidth requirements of wireline links increase, extensive digital equalization techniques are required to compensate for the high-frequency channel ...

EPFL2021

Low Noise Clock Generation: Modeling, Analysis and Implementation

Duygu Kostak

The aim of this thesis is to implement, analyze and improve the selected low noise clock generation and distribution techniques for ADC implementations. The thesis is divided into two parts. The first part focuses on the sampling phase generation and distr ...

EPFL2021

Engineering Breakdown Probability Profile for PDP and DCR Optimization in a SPAD Fabricated in a Standard 55nm BCD Process

Edoardo Charbon, Claudio Bruschini, Ekin Kizilkan, Pouyan Keshavarzian, Francesco Gramuglia, Myung Jae Lee

CMOS Single-Photon Avalanche Diodes (SPADs) have broken into the mainstream by enabling the adoption of imaging, timing, and security technologies in a variety of applications within the consumer, medical and industrial domains. The continued scaling of te ...

2021

GC-eDRAM with Body-Bias Compensated Readout and Error Detection in 28nm FD-SOI

Andreas Peter Burg, Adam Shmuel Teman, Robert Giterman, Andrea Bonetti

Gain-cell embedded DRAM (GC-eDRAM) is an attractive alternative to conventional SRAM due to its high-density, low-leakage, and inherent two-ported functionality. However, its dynamic storage mechanism requires power-hungry refresh cycles to maintain data. ...

IEEE2020

Sweat monitoring with CMOS compatible technology: ISFETS and beyond

Francesco Bellando

In recent years, sweat has gained increasing attention from the scientific community as a new analyte for health monitoring. The main advantage with respect to the "Gold Standard" for laboratory analysis, i.e. blood, is of course the possibility of perform ...

EPFL2020

A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET

Andreas Peter Burg, Cosimo Aprile, Yusuf Leblebici, Alessandro Cevrero, Gain Kim, Lukas Kull, Ilter Ozkaya, Thomas Toifl

This article introduces a wireline receiver (RX) data-path employing discrete multi-tone (DMT) modulation for communicating over electrical links. The DMT RX incorporates a fully digital equalization data-path, with a synthesized and automatically placed a ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

Gain-Cell Embedded DRAMs: Modeling and Design Space

Andreas Peter Burg, Adam Shmuel Teman, Robert Giterman, Andrea Bonetti

Among the different types of DRAMs, gain-cell embedded DRAM (GC-eDRAM) is a compact, low-power and CMOS-compatible alternative to conventional SRAM. GC-eDRAM achieves high memory density as it relies on a storage cell that can be implemented with as few as ...

IEEE2020

Characterization and Analysis of On-Chip Microwave Passive Components at Cryogenic Temperatures

Edoardo Charbon, Andrea Ruffino, Fabio Sebastiano

This paper presents the characterization and modeling of microwave passive components in TSMC 40-nm bulk CMOS, including metal-oxide-metal (MoM) capacitors, transformers, and resonators, at deep cryogenic temperatures (4.2 K). To extract the parameters of ...

2020

Gain-Cell Embedded DRAMs: Modeling and Design Space

Andreas Peter Burg, Adam Shmuel Teman, Robert Giterman, Andrea Bonetti

Among the different types of dynamic random-access memories (DRAMs), gain-cell embedded DRAM (GC-eDRAM) is a compact, low-power, and CMOS-compatible alternative to conventional static random-access memory (SRAM). GC-eDRAM achieves high memory density, as i ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

High fill-factor miniaturized SPAD arrays with a guard-ring-sharing technique

Edoardo Charbon, Kazuhiro Morimoto

We present a novel guard-ring-sharing technique to push the limit of SPAD pixel miniaturization, and to demonstrate the operation of SPAD arrays with a 2.2 mu m-pitch, the smallest ever reported. Device simulation and preliminary tests suggest that the opt ...

2020

GC-eDRAM With Body-Bias Compensated Readout and Error Detection in 28-nm FD-SOI

Andreas Peter Burg, Adam Shmuel Teman, Robert Giterman, Andrea Bonetti

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2019

Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures

Edoardo Charbon, Fabio Sebastiano

Cryogenic device models are essential for the reliable design of the cryo-CMOS interface that enables large-scale quantum computers. In this paper, mismatch characterization and modeling of a 40-nm bulk CMOS process over the 4.2-300 K temperature range is ...

IEEE2019

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