Publications related to SystemVerilog

Highly Parallel RTL Simulation

Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL. As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and ...

EPFL2024

A 3.3-Gb/s SPAD-Based Quantum Random Number Generator

Edoardo Charbon, Pouyan Keshavarzian, Francesco Gramuglia, Mario Stipcevic

Quantum random number generators (QRNGs) are a burgeoning technology used for a variety of applications, including modern security and encryption systems. Typical methods exploit an entropy source combined with an extraction or bit generation circuit in or ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2023

Analytic modelling of passive microfluidic mixers

Jean-Michel Sallese, Christophe Lallement

This paper deals with a new analytical model for microfluidic passive mixers. Two common approaches already exist for such a purpose. On the one hand, the resolution of the advection-diffusion-reaction equation (ADRE) is the first one and the closest to ph ...

AMER INST MATHEMATICAL SCIENCES-AIMS2022

Straight to the Point: Intra- and Intercluster LUT Connections to Mitigate the Delay of Programmable Routing

Paolo Ienne, Grace Zgheib, Stefan Nikolic

Technology scaling makes metal delay ever more problematic, but routing between Look-Up Tables (LUTs) still passes through a series of transistors. It seems wise to avoid the corresponding delay whenever possible. Direct connections between LUTs, both with ...

ASSOC COMPUTING MACHINERY2020

CASSIS: Characterization with Adaptive Sample-Size Inferential Statistics Applied to Inexact Circuits

Vincent Frédéric Camus

To design faster and more energy-efficient systems, numerous inexact arithmetic operators have been proposed, generally obtained by modifying the logic structure of conventional circuits. However, as the quality of service of an application has to be ensur ...

2018

FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs

Giovanni De Micheli, Xifan Tang, Pierre-Emmanuel Julien Marc Gaillardon, Edouard Giacomin

In this paper, we developed a simulation-based architecture evaluation framework for field-programmable gate arrays (FPGAs), called FPGA-SPICE, which enables automatic layout-level estimation and electrical simulations of FPGA architectures. FPGA-SPICE can ...

2018

System Level simulation framework for the ASICs development of a novel particle physics detector

Yusuf Leblebici, Alessandro Caratelli, Davide Ceresa, Simone Scarfì

The simulation of the passage of particles through matter using Monte Carlo methods is broadly used in the development of particle detectors for high energy physics experiments. To develop the readout electronics for the Compact Muon Solenoid (CMS) experim ...

IEEE2018

Post-P&R Performance and Power Analysis for RRAM-based FPGAs

Giovanni De Micheli, Xifan Tang, Pierre-Emmanuel Julien Marc Gaillardon, Edouard Giacomin

Resistive Random Access Memory (RRAM)-based FPGAs are predicted to outperform conventional FPGAs architectures in area, delay and power over a wide range of voltage operations, allowing novel energy-quality trade-offs for reconfigurable computing. The oppo ...

2018

Virtual Prototyping Methodology for Power Automation Cyber-Physical-Systems

Juan Sebastian Rodriguez Estupinan

In this thesis, the author proposes a circular system development model which considers all the stages in a typical development process for industrial systems. In particular, the present work shows that the use of virtual prototyping at early stages of the ...

EPFL2017

Circuit Design, Architecture and CAD for RRAM-based FPGAs

Xifan Tang

Field Programmable Gate Arrays (FPGAs) have been indispensable components of embedded systems and datacenter infrastructures. However, energy efficiency of FPGAs has become a hard barrier preventing their expansion to more application contexts, due to two ...

EPFL2017

Hierarchical Reversible Logic Synthesis Using LUTs

Giovanni De Micheli, Mathias Soeken

Today's rapid advances in the physical implementation of quantum computers demand for scalable synthesis methods in order to map practical logic designs to quantum architectures. We present a synthesis algorithm for quantum computing based on k-LUT network ...

IEEE2017

Algorithmic Verification of Component-based Systems

Qiang Wang

This dissertation discusses algorithmic verification techniques for concurrent component-based systems modeled in the Behavior-Interaction-Priority (BIP) framework with both bounded and unbounded concurrency. BIP is a component framework for mixed software ...

EPFL2017

Functional BIP: Embedding connectors in functional programming languages

Romain Edelmann, Joseph Sifakis, Simon Bliudze

This paper presents a theoretical foundation for functional language implementations of Behaviour–Interaction–Priority (BIP). We introduce a set of connector combinators describing synchronisation, data transfer, priorities and dynamicity in a principled w ...

Elsevier Science Inc2017

FudgeFactor: Syntax-Guided Synthesis for Accurate RTL Error Localization and Correction

Paolo Ienne, Barbara Jobstmann, David Novo Bruna, Andrew James Becker, Mohsen A A Ewaida

Functional verification occupies a significant amount of the digital circuit design cycle. In this paper, we present a novel approach to improve circuit debugging which not only localizes errors with high confidence, but can also provide semantically-meani ...

Springer2015

Interpolation for Synthesis on Unbounded Domains

Viktor Kuncak, Régis William Blanc

Synthesis procedures compile relational specifications into functions. In addition to bounded domains, synthesis procedures are applicable to domains such as mathematical integers, where the domain and range of relations and synthesized code is unbounded. ...

Ieee2013

Process/Design Co-optimization of Regular Logic Tiles for Double-Gate Silicon Nanowire Transistors

Giovanni De Micheli, Davide Sacchetto, Yusuf Leblebici, Pierre-Emmanuel Julien Marc Gaillardon, Jian Zhang, Shashi Kanth Bobba, Michele De Marchi

Ambipolar transistors with on-line configurability to n-type and p-type polarity are desirable for future integrated circuits. Regular logic tiles have been recognized as an efficient layout fabric for ambipolar devices. In this work, we present a process/ ...

2012

VHDL-AMS Model of an Electrochemical Cell to Design VLSI Bio-Chips

Giovanni De Micheli, Sandro Carrara, Yusuf Leblebici, Alain Vachoux, Marialaura Beltrandi

This paper presents a new VHDL-AMS behavioral model of an electrochemical cell suitable for the design of VLSI bio-chips. Existing models are mainly equivalent circuit macromodels using electrical primitives, which hardly fit the actual behavior of biosens ...

2011

Efficient Modelling and Simulation Methodology for the Design of Heterogeneous Mixed-Signal Systems on Chip

Torsten Mähne

Systems on Chip (SoCs) and Systems in Package (SiPs) are key parts of a continuously broadening range of products, from chip cards and mobile phones to cars. Besides an increasing amount of digital hardware and software for data processing and storage, the ...

EPFL2011

Physics-based compact model for ultra-scaled FinFETs

Jean-Michel Sallese, Ashkhen Yesayan, Christophe Lallement

A physical and explicit compact model for lightly doped FinFETs is presented. This design-oriented model is valid for a large range of silicon Fin widths and lengths, using only a very few number of model parameters. The quantum mechanical effects (QMEs), ...

2011

Formal Analysis of SystemC Designs in Process Algebra

Hossein Hojjat

SystemC is an IEEE standard system-level language used in hardware/software co-design and has been widely adopted in the industry. This paper describes a formal approach to verifying SystemC designs by providing a mapping to the process algebra mCRL2. Our ...

2011