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Related publications (31)

Exploring brain-inspired multi-core heterogeneous hardware templates for low-power biomedical embedded systems

Benoît Walter Denkinger

The miniaturization of integrated circuits (ICs) and their higher performance and energy efficiency, combined with new machine learning algorithms and applications, have paved the way to intelligent, interconnected edge devices. In the medical domain, they ...

EPFL2023

Systematic design of a multi-input multi-output controller by model-based decoupling: a demonstration on TCV using multi-species gas injection

Basil Duval, Christian Gabriel Theiler, Cristian Galperti, Artur Perek

In this paper, we present the first results of a systematically designed multi-input multi-output gas-injection controller on Tokamak a Configuration Variable (TCV). We demonstrate the simultaneous real-time control of the NII emission front position and l ...

IOP Publishing Ltd2023

Hardware-Software co-design Methodologies for Edge AI Optimization

Flavio Ponzina

ML-based edge devices may face memory and computational errors that affect applications' reliability and performance. These errors can be the result of particular working conditions (e.g., radiation areas in physical experiments or avionics) or could be th ...

EPFL2023

Automated Design Appraisal: Estimating Real Estate Price Growth and Value at Risk Due to Local Development

Adam Robert Swietek

Financial criteria in architectural design evaluation are limited to cost performance. Here, I introduce a method – Automated Design Appraisal (ADA) – to predict the market price of a generated building design concept within a local urban context. Integrat ...

2023

A Deep-Learning Approach to Side-Channel Based CPU Disassembly at Design Time

Mirjana Stojilovic

Side-channel CPU disassembly is a side-channel attack that allows an adversary to recover instructions executed by a processor. Not only does such an attack compromise code confidentiality, it can also reveal critical information on the system’s internals. ...

IEEE2022

Thermal and Power-Aware Run-Time Performance Management of 3D MPSoCs with Integrated Flow Cell Arrays

David Atienza Alonso, Giovanni Ansaloni, Marina Zapater Sancho, Alexandre Sébastien Julien Levisse, Halima Najibi

Flow Cell Arrays (FCA) technology employs microchannels filled with an electrolytic fluid to concurrently provide cooling and power generation to integrated circuits (ICs). This solution is particularly appealing for Three-Dimensional Multi-Processor Syste ...

2022

Design and management of three-dimensional multi-processor systems-on-chip with integrated flow cell arrays

Halima Najibi

Three-Dimensional Multi-Processor Systems-on-Chip (3D MPSoCs) are promising solutions for highly intensive Artificial Intelligence (AI) and Big Data applications. They combine remarkably dense computation capabilities and massive communication bandwidths. ...

EPFL2022

A 500 x 500 Dual-Gate SPAD Imager With 100% Temporal Aperture and 1 ns Minimum Gate Length for FLIM and Phasor Imaging Applications

Edoardo Charbon, Claudio Bruschini, Andrei Ardelean, Paul Mos, Arin Can Ülkü, Michael Alan Wayne

In this article, we report on SwissSPAD3 (SS3), a 500 x 500 pixel single-photon avalanche diode (SPAD) array, fabricated in 0.18-mu m CMOS technology. In this sensor, we introduce a novel dual-gate architecture with two contiguous temporal windows, or gate ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Source Reconstruction Method Using Phase-Less Magnetic Near-Field Measurements: Application of the Method of Moment with Roof-Top Basis Functions

Marcos Rubinstein, Hamidreza Karami

Source reconstruction methods have many applications such as antenna diagnosis, calculating far-field radiated emissions, and identifying incompatible sources on integrated circuits or printed circuit boards. In this paper, the Gerchberg-Saxton algorithm i ...

IEEE2022

Optimizing Lattice-based Post-Quantum Cryptography Codes for High-Level Synthesis

Francesco Regazzoni, Andrea Guerrieri, Andres Upegui

High-level synthesis is a mature Electronics Design Automation (EDA) technology for building hardware design in a short time. It produces automatically HDL code for FPGAs out of C/C++, bridging the gap from algorithm to hardware. Nevertheless, sometimes th ...

IEEE2022

New Insights for Parasitic Effects of Label-Free Biosensors Based on Capacitive Micromachined Ultrasonic Transducers

Sandro Carrara, Zhengwen Jiang, Yihe Zhao, Jie Li

Capacitive micromachined ultrasonic transducers (CMUTs) are regarded as an attractive candidate in bio-applications such as imaging and molecule monitoring. However, the previous researches on biochemical sensing are mostly air-coupled application based on ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

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