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Related publications (26)

Self-Assembled Liquid-Gated Zinc Oxide Nanowire Transistors : Fabrication and Sensing Operation

Vivek Pachauri

This thesis aims at the site-specific realization of self-assembled field-effect transistors (FETs) based on semiconducting Zinc oxide NWs and their application towards chemical and bio-sensing in liquid medium. At first, a solution based growth method for ...

EPFL2011

Graphene-based Field-effect Transistors

Adarsh Singh Sagar

With transistors set to reach their smallest possible size in the next decade, the silicon chip is likely to change dramatically, or be replaced entirely. The transistor industry's path which has been largely shaped by Gordon Moore's famous prediction that ...

EPFL2011

The Single-Electron Bipolar Avalanche Transistor

Marc Lany

We present a new electronic device – the single-electron bipolar avalanche transistor (SEBAT) – which allows for the detection of single charges with a bandwidth typically above 1 GHz, exceeding by far the bandwidth of other room-temperature single-electro ...

EPFL2010

Realization of the Conscience Mechanism in CMOS Implementation of Winner-Takes-All Self-Organizing Neural Networks

Rafal Tomasz Dlugosz

This paper presents a complementary metal–oxide– semiconductor (CMOS) implementation of a conscience mechanism used to improve the effectiveness of learning in the winnertakes- all (WTA) artificial neural networks (ANNs) realized at the transistor level. T ...

Institute of Electrical and Electronics Engineers2010

A circuit-level substrate current model for smart-power ICs

Maher Kayal, Jean-Michel Sallese, François Krummenacher, Marc Pastre, Fabrizio Lo Conte

This paper presents a new modeling methodology accounting for generation and propagation of minority carriers that can be used directly in circuit-level simulators in order to estimate coupled parasitic currents. The model is based on a new compact model o ...

IEEE Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2009

Dynamic Thermal Management in 3D Multicore Architectures

David Atienza Alonso, Yusuf Leblebici, José Luis Ayala Rodrigo, Ayse Kivilcim Coskun

Technology scaling has caused the feature sizes to shrink continuously, whereas interconnects, unlike transistors, have not followed the same trend. Designing 3D stack architectures is a recently proposed approach to overcome the power consumption and dela ...

IEEE and ACM2009

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