Publications related to Delay slot

WarpAttack: Bypassing CFI through Compiler-Introduced Double-Fetches

Mathias Josef Payer, Flavio Toffalini, Luca Di Bartolomeo, Jianhao Xu

Code-reuse attacks are dangerous threats that attracted the attention of the security community for years. These attacks aim at corrupting important control-flow transfers for taking control of a process without injecting code. Nowadays, the combinations o ...

IEEE COMPUTER SOC2023

Micro BTB: A High Performance and Storage Efficient Last-Level Branch Target Buffer for Servers

Vishal Gupta

High-performance branch target buffers (BTBs) and the L1I cache are key to high-performance front-end. Modern branch predictors are highly accurate, but with an increase in code footprint in modern-day server workloads, BTB and L1I misses are still frequen ...

ASSOC COMPUTING MACHINERY2022

Distributed Computing with Modern Shared Memory

Mihail Igor Zablotchi

In this thesis, we revisit classic problems in shared-memory distributed computing through the lenses of (1) emerging hardware technologies and (2) changing requirements. Our contributions consist, on the one hand, in providing a better understanding of th ...

EPFL2020

FLeet: Online Federated Learning via Staleness Awareness and Performance Prediction

Rachid Guerraoui, Anne-Marie Kermarrec, Rhicheek Patra, Georgios Damaskinos, Vlad-Tiberiu Nitu

Federated Learning (FL) is very appealing for its privacy benefits: essentially, a global model is trained with updates computed on mobile devices while keeping the data of users local. Standard FL infrastructures are however designed to have no energy or ...

Association for Computing Machinery2020

Linebacker: Preserving Victim Cache Lines in Idle Register Files of GPUs

Yunho Oh

Modern GPUs suffer from cache contention due to the limited cache size that is shared across tens of concurrently running warps. To increase the per-warp cache size prior techniques proposed warp throttling which limits the number of active warps. Warp thr ...

ASSOC COMPUTING MACHINERY2019

Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains

Giovanni De Micheli, Paolo Ienne, Mathias Soeken, Grace Zgheib, Xifan Tang, Pierre-Emmanuel Julien Marc Gaillardon, Ana Petkovska, Luca Gaetano Amarù, Zhufei Chu

Hard-wired carry chains in FPGAs are designed to improve efficiency of important arithmetic primitives. Although they are proven to be effective for arithmetic-rich functions, there are very few studies on the optimization opportunities of carry chains for ...

ACM2017

Apodization Scheme for Hardware-Efficient Beamformer

Jean-Philippe Thiran, Giovanni De Micheli, Federico Angiolini, Marcel Arditi, Aya Mohamed Naguib Ahmed Ibrahim

3D ultrasound is an emerging diagnostic technique that extends standard ultrasound imaging by capturing volumes, instead of planes. This brings completely new diagnostic opportunities, among which the possibility of disjoining image acquisition and analysi ...

Ieee2016

Single-FPGA 3D Ultrasound Beamformer

Jean-Philippe Thiran, Giovanni De Micheli, Federico Angiolini, Marcel Arditi, Aya Mohamed Naguib Ahmed Ibrahim, Ahmet Caner Yüzügüler

In medical diagnosis, ultrasound (US) imaging is one of the most common, safe, and powerful techniques. Volumetric (3D) US imaging, an emerging technique, is even more attractive than standard 2D imaging, as it allows for imaging without the local presence ...

Ieee2016

The Movement Error Rate for Evaluation of Machine Learning Methods for sEMG-based Hand Movement Classification

Barbara Caputo

There has been increasing interest in applying learning algorithms to improve the dexterity of myoelectric prostheses. In this work, we present a large-scale benchmark evaluation on the second iteration of the publicly released NinaPro database, which cont ...

2014

Pipeline Synthesis and Optimization of FPGA-based Video Processing Applications with CAL

Marco Mattavelli, Anatoly Prihozhy, Ab Al Hadi Bin Ab Rahman

This paper describes a pipeline synthesis and optimization technique that increases data throughput of FPGA-based system using minimum pipeline resources. The technique is applied on \CAL dataflow language, and designed based on relations, matrices and gra ...

Hindawi Publishing Corporation2011

Dynamic Thermal Management in 3D Multicore Architectures

David Atienza Alonso, Yusuf Leblebici, José Luis Ayala Rodrigo, Ayse Kivilcim Coskun

Technology scaling has caused the feature sizes to shrink continuously, whereas interconnects, unlike transistors, have not followed the same trend. Designing 3D stack architectures is a recently proposed approach to overcome the power consumption and dela ...

IEEE and ACM2009

Issues in petabyte data indexing, retrieval and analysis

Sébastien Ponce

We propose several methods for speeding up the processing of particle physics data on clusters of PCs. We present a new way of indexing and retrieving data in a high dimensional space by making use of two levels of catalogues enabling an efficient data pre ...

EPFL2006