Adder (electronics)

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Related publications (29)

Improving FPGA Performance for Carry-Save Arithmetic

Paolo Ienne, Ajay Kumar Verma, Philip Brisk, Hadi Parandeh Afshar

The selective use of carry-save arithmetic, where appropriate, can accelerate a variety of arithmetic-dominated circuits. Carry-save arithmetic occurs naturally in a variety of DSP applications, and further opportunities to exploit it can be exposed throug ...

2010

Methodology for the Digital Calibration of Analog Circuits and Systems Using Sub-binary Radix DACs

Maher Kayal, Marc Pastre

This paper presents a methodology for digitally calibrating analog circuits and systems. Based on the detection of an imperfection by a simple comparator, a successive approximations algorithm tunes a compensation current. The latter is generated by a sub- ...

2010

Arithmetic Optimization for Custom Instruction Set Synthesis

Paolo Ienne, Philip Brisk, Ajay Kumar Verma, Yi Zhu

One of the ways that custom instruction set extensions can improve over software execution is through the use of hardware structures that have been optimized at the arithmetic level. Arithmetic hardware, in many cases, can be partitioned into networks of f ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2009

Exploiting Fast Carry-Chains Of Fpgas For Designing Compressor Trees

Paolo Ienne, Philip Brisk, Hadi Parandeh Afshar

Fast carry chains featuring dedicated adder circuitry is a distinctive feature of modern FPGAs. The carry chains bypass the general routing network and are embedded in the logic blocks of FPGAs for fast addition. Conventional intuition is that such carry c ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2009

Optimization of Nanoelectronic Systems Reliability under Massive Defect Density Using Distributed R-Fold Modular Redundancy

Alexandre Schmid, Yusuf Leblebici, Milos Stanisavljevic

The theoretical analysis of R-fold modular redundancy with distributed voters - distributed R-fold modular redundancy in terms of reliability is presented for the first time to the best of author's knowledge. This technique is compared in terms of resistan ...

IEEE Computer Soc Press, Customer Service Center, Po Box 3014, 10662 Los Vaqueros Circle, Los Alamitos, Ca 90720-1264 Usa2009

Methodology for the Digital Calibration of Analog Circuits and Systems Using Sub-binary Radix DACs

Maher Kayal, Marc Pastre

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2009

Turbo-Like Structures for Chaos Encoding and Decoding

Martin Hasler, Slobodan Kozic, Francisco Javier Escribano Aparicio

In this paper, we explain how to build a turbo-like structure with binary inputs and chaotic outputs for efficient coding and decoding in additive white Gaussian noise (AWGN). We analyze the convergence of the decoding algorithm, the performance in the err ...

2009

Variable latency speculative addition: A new paradigm for arithmetic circuit design

Paolo Ienne, Philip Brisk, Ajay Kumar Verma

Adders are one of the key components in arithmetic circuits. Enhancing their performance can significantly improve the quality of arithmetic designs. This is the reason why the theoretical lower bounds on the delay and area of an adder have been analysed, ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2008

Optimization of nanoelectronic systems' reliability under massive defect density using Cascaded R-fold modular redundancy

Alexandre Schmid, Yusuf Leblebici, Milos Stanisavljevic

The theoretical analysis of R-fold modular redundancy, cascaded R-fold modular redundancy and NAND multiplexing is presented and these fault-tolerant techniques are compared in terms of resistance to massive levels of defect density. Optimal cluster size a ...

2008

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