Publications related to Circuit underutilization

Active Wire Fences for Multitenant FPGAs

Mirjana Stojilovic, Ognjen Glamocanin, Stasa Kostic, Andela Kostic

When spatially shared among multiple tenants, field-programmable gate arrays (FPGAs) are vulnerable to remote power side-channel analysis attacks. Using carefully crafted on-chip voltage sensors, adversaries can extract secrets (e.g., encryption keys or th ...

2023

Practical Implementations of Remote Power Side-Channel and Fault-Injection Attacks on Multitenant FPGAs

Francesco Regazzoni, Mirjana Stojilovic, Dina Gamaleldin Ahmed Shawky Mahmoud, Ognjen Glamocanin

Cloud computing environments increasingly provision FPGAs because of their fine-grained, highly parallel, and flexible hardware architecture. The availability of FPGAs in the cloud fueled research on the security risks associated with exposing FPGA fabric ...

Springer, Cham2023

Learning With Your PETS

Drazen Dujic, Andrea Cervone, Jules Christian Georges Macé, Max Dupont, Renan Pillon Barcelos

Recently, we published an article [1] presenting how the Power Electronics course at the bachelor level is organized by the Power Electronics Laboratory and taught at Ecole Polytechnique Fédérale de Lausanne, EPFL, Switzerland. For those avid readers who m ...

2023

Evaluating, Exploiting, and Hiding Power Side-Channel Leakage of Remote FPGAs

Ognjen Glamocanin

The pervasive adoption of field-programmable gate arrays (FPGAs) in both cyber-physical systems and the cloud has raised many security issues. Being integrated circuits, FPGAs are susceptible to fault and power side-channel attacks, which require physical ...

EPFL2023

A Visionary Look at the Security of Reconfigurable Cloud Computing

Francesco Regazzoni, Mirjana Stojilovic

Field-programmable gate arrays (FPGAs) have become critical components in many cloud computing platforms. These devices possess the fine-grained parallelism and specialization needed to accelerate applications ranging from machine learning to networking an ...

2023

Automating the Design of Programmable Interconnect for Reconfigurable Architectures

Stefan Nikolic

With Moore's law coming to an end, increasingly more hope is being put in specialized hardware implemented on reconfigurable architectures such as Field-Programmable Gate Arrays (FPGAs). Yet, it is often neglected that these architectures themselves experi ...

EPFL2023

A 500 x 500 Dual-Gate SPAD Imager With 100% Temporal Aperture and 1 ns Minimum Gate Length for FLIM and Phasor Imaging Applications

Edoardo Charbon, Claudio Bruschini, Andrei Ardelean, Paul Mos, Arin Can Ülkü, Michael Alan Wayne

In this article, we report on SwissSPAD3 (SS3), a 500 x 500 pixel single-photon avalanche diode (SPAD) array, fabricated in 0.18-mu m CMOS technology. In this sensor, we introduce a novel dual-gate architecture with two contiguous temporal windows, or gate ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Assessment of the Bundle SNSPD Plus FPGA-Based TDC for High-Performance Time Measurements

Christophe Marcel Georges Galland, Andrea Costa, Santiago Tarrago Velez

Counting single photons and measuring their arrival time is of crucial importance for imaging and quantum applications that use single photons to outperform classical techniques. The investigation of the coincidence, i.e. correlation, between photons can b ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

DFAulted: Analyzing and Exploiting CPU Software Faults Caused by FPGA-Driven Undervolting Attacks

Mirjana Stojilovic, Dina Gamaleldin Ahmed Shawky Mahmoud, David Dervishi

Field-programmable gate arrays (FPGAs) combine hardware reconfigurability with a high degree of parallelism. Consequently, FPGAs offer performance gains and power savings for many applications. A recent trend has been to leverage the hardware versatility o ...

2022

Low-Power Artificial Neural Network Perceptron Based on Monolayer MoS2

Aleksandra Radenovic, Andras Kis, Mukesh Kumar Tripathi, Guilherme Migliato Marega, Zhenyu Wang

Machine learning and signal processing on the edge are poised to influence our everyday lives with devices that will learn and infer from data generated by smart sensors and other devices for the Internet of Things. The next leap toward ubiquitous electron ...

2022

Low-Latency High-Bandwidth Circuit and System Design for Trigger Systems in High Energy Physics

Marcos Vinícius Silva Oliveira

The increasing luminosity in HEP (High Energy Physics) colliders demands trigger systems to be more selective. First, more information from the detector is routed to the trigger system. Second, larger parts of this information are processed together. These ...

EPFL2021

Synthesizing General-Purpose Code Into Dynamically Scheduled Circuits

Paolo Ienne, Andrea Guerrieri, Lana Josipovic

Since their inception more than thirty years ago, field-programmable gate arrays (FPGAs) have been widely used to implement a myriad of applications from different domains. As a result of their low-level hardware reconfigurability, FPGAs have much faster d ...

2021

Optimization Methods for Control: From Embedded Programmable Hardware to Data-Driven Process Optimization

Harsh Ambarishkumar Shukla

The research community has been making significant progress in hardware implementation, numerical computing and algorithm development for optimization-based control. However, there are two key challenges that still have to be overcome for optimization-base ...

EPFL2021

Energy-Efficient Design Techniques for High-Speed Wireline Serial Links

Firat Çelik

The exponential growth in computing power and multimedia services has caused a tremendous increase in data traffic in recent years. This increase in data traffic brings a strong demand for data bandwidth of electrical input/output (I/O) links and pushes th ...

EPFL2021

JPEG XS-A New Standard for Visually Lossless Low-Latency Lightweight Image Coding

Touradj Ebrahimi

Joint Photographic Experts Group (JPEG) XS is a new International Standard from the JPEG Committee (formally known as ISO/International Electrotechnical Commission (IEC) JTC1/SC29/WG1). It defines an interoperable, visually lossless low-latency lightweight ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2021

A Review of Microelectronic Systems and Circuit Techniques for Electrical Neural Recording Aimed at Closed-Loop Epilepsy Control

Alexandre Schmid, Reza Ranjandish

Closed-loop implantable electronics offer a new trend in therapeutic systems aimed at controlling some neurological diseases such as epilepsy. Seizures are detected and electrical stimulation applied to the brain or groups of nerves. To this aim, the signa ...

2020

Design and experimental validation of an FPGA-based PMU simultaneously compliant with P and M performance classes

Mario Paolone, Asja Derviskadic

Low-inertia grids are characterized by high shares of harmonic and inter-harmonic distortion, produced by the inverters that interface non-conventional generation assets to the electrical grid. These interfering tones largely compromise synchrophasor estim ...

Elsevier2020

Electromagnetic Time Reversal: Theory, Application to Fault Location in Power Networks and Experimental Validation

Zhaoyang Wang

The time-reversal invariance is readily described and universally embodied in most laws of nature, either in a strict or in a soft sense. Based on this underlying physical principle, time-reversal theory has been theoretically and experimentally studied in ...

EPFL2020

Efficient random number generation techniques for CMOS single-photon avalanche diode array exploiting fast time tagging units

Edoardo Charbon, Samuel Burri

This work presents a technique to produce random bits by exploiting single-photon time of arrival. Two quantum random number generator (QRNG) devices based on the field programmable gate array (FPGA) technology are presented: Randy, which uses one discrete ...

AMER PHYSICAL SOC2020

Extending Boolean Methods for Scalable Logic Synthesis

Giovanni De Micheli, Mathias Soeken, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù, Eleonora Testa

In recent years, Boolean methods in logic synthesis have been drawing the attention of EDA researchers due to the continuous push to advance quality of results. Boolean methods require high computational cost, as they rely on complete functional properties ...

2020