Publications related to EEPROM

Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference

David Atienza Alonso, Giovanni Ansaloni, Alexandre Sébastien Julien Levisse, Marco Antonio Rios, Flavio Ponzina

By supporting the access of multiple memory words at the same time, Bit-line Computing (BC) architectures allow the parallel execution of bit-wise operations in-memory. At the array periphery, arithmetic operations are then derived with little additional o ...

2023

2D Nanosystems: Applications of 2D Semiconductors for In-Memory Computing

Guilherme Migliato Marega

Machine learning and data processing algorithms have been thriving in finding ways of processing and classifying information by exploiting the hidden trends of large datasets. Although these emerging computational methods have become successful in today's ...

EPFL2023

How to Achieve Large-Area Ultra-Fast Operation of MoS 2 Monolayer Flash Memories?

Aleksandra Radenovic, Andras Kis, Mukesh Kumar Tripathi, Asmund Kjellegaard Ottesen, Yanfei Zhao, Guilherme Migliato Marega, Zhenyu Wang, Hyungoo Ji

Memory devices have returned to the spotlight due to increasing interest in using in-memory computing architectures to make data-driven algorithms more energy-efficient. One of the main advantages of this architecture is the efficient performance of vector ...

2023

Impact of Interface Traps in Floating-Gate Memory Based on Monolayer MoS2

Andras Kis, Guilherme Migliato Marega

Two-dimensional materials (2DMs) have found potential applications in many areas of electronics, such as sensing, memory systems, optoelectronics, and power. Despite an intense experimental work, the literature is lacking of accurate modeling of nonvolatil ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Perovskite Flash Memory with a Single-Layer Nanofloating Gate

Mohammad Khaja Nazeeruddin, Tom Theodorus Antonius Lummen, Peng Gao, Hobeom Kim

Here we use triple-cation metal-organic halide perovskite single crystals for the transistor channel of a flash memory device. Moreover, we design and demonstrate a 10 nm thick single-layer nanofloating gate. It consists of a ternary blend of two organic s ...

2020

OneFile: A Wait-free Persistent Transactional Memory

Nachshon Cohen, Pascal Felber

A persistent transactional memory (PTM) library provides an easy-to-use interface to programmers for using byte-addressable non-volatile memory (NVM). Previously proposed PTMs have, so far, been blocking. We present OneFile, the first wait-free PTM with in ...

IEEE COMPUTER SOC2019

Resistive Switching Memory Architecture Based on Polarity Controllable Selectors

Alexandre Sébastien Julien Levisse, Pierre-Emmanuel Julien Marc Gaillardon

With the continuous scaling of CMOS technology, integrating an embedded high-density non-volatile memory appears to be more and more costly and technologically challenging. Beyond floating-gate memory technologies, bipolar resistive random access memories ...

2018

Prospects for energy-efficient edge computing with integrated HfO2-based ferroelectric devices

Mihai Adrian Ionescu, Igor Stolichnov

Edge computing requires highly energy efficient microprocessor units with embedded non-volatile memories to process data at IoT sensor nodes. Ferroelectric non-volatile memory devices are fast, low power and high endurance, and could greatly enhance energy ...

IEEE2018

A phase-change memory model for neuromorphic computing

Irem Boybat Kara, Evangelos Eleftheriou, Abu Sebastian

Phase-change memory (PCM) is an emerging non-volatile memory technology that is based on the reversible and rapid phase transition between the amorphous and crystalline phases of certain phase-change materials. The ability to alter the conductance levels i ...

AMER INST PHYSICS2018

Resistive random access memory based multiplexers and field programmable gate arrays

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Xifan Tang, Gain Kim, Edouard Giacomin

Resistive random access memory (RRAM) based multiplexers and field programmable gate arrays (FPGAs) are provided. The RRAM-based multiplexers and FPGAs include a 4T1R programming structure to program the RRAMs. The programming structure includes two progra ...

2018

Critical scattering and incommensurate phase transition in antiferroelectric PbZrO3 under pressure

Alexander Tagantsev

Antiferroelectric lead zirconate is the key ingredient in modern ferroelectric and piezoelectric functional solid solutions. By itself it offers opportunities in new-type non-volatile memory and energy storage applications. A highly useful and scientifical ...

Springer Nature2017

Fabrication, Characterization and Integration of Resistive Random Access Memories

Jury Sandrini

The functionalities and performances of today's computing systems are increasingly dependent on the memory block. This phenomenon, also referred as the Von Neumann bottleneck, is the main motivation for the research on memory technologies. Despite CMOS tec ...

EPFL2017

Nanoionics Phenomena and Devices with Oxide Thin Films

Mahmoud Hadad

The number of studies on solid state ionic thin films (Nanoionics) has increased dramatically over last decades due to their high potential in micro and nanoscale technologies. Micro solid oxide fuel cells (micro-SOFC), and resistive switching memories (Re ...

EPFL2017

Effect of metal buffer layer and thermal annealing on HfOx-based ReRAMs

Elmira Shahrabi, Igor Krawczuk, Yusuf Leblebici, Jury Sandrini, Behnoush Attarimashalkoubeh

In this paper, we investigate different methods and approaches in order to improve the electrical characteristics of Pt/HfOx/TiN ReRAM devices. We discuss the improvement of the ReRAM electrical characteristics after the insertion of a Hf and Ti buffer lay ...

Ieee2016

Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications

Andreas Peter Burg, Adam Shmuel Teman, Robert Giterman, Pascal Andreas Meinerzhagen

Logic compatible gain cell (GC) embedded DRAM (eDRAM) arrays are considered an alternative to SRAM due to their small size, non-ratioed operation, low static leakage, and 2-port functionality. However, traditional GC-eDRAM implementations require boosted c ...

Ieee-Inst Electrical Electronics Engineers Inc2016

Chip-Level CMOS Co-Integration of ReRAM-Based Non-Volatile Memories

Elmira Shahrabi, Yusuf Leblebici, Jury Sandrini, Tugba Demirci, Mahmoud Hadad, Behnoush Attarimashalkoubeh

This work reports a technique to fabricate ReRAM crossbar arrays co-integrated with fully finished 180 nm CMOS technology chips. The proposed integration method enables low- cost ReRAM-CMOS integration and allows the rapid prototyping of complete memory sy ...

Ieee2016

Charge-transport properties of monolayer MoS2 at the interface with dielectric materials

Simone Bertolazzi

Two-dimensional (2D) semiconductors, consisting of single-sheets of layered transition metal dichalcogenides (TMD), are attracting enormous interest from both fundamental science and technology. Monolayer molybdenum disulfide (MoS2), a typical example from ...

EPFL2015

Re-writing scheme for solid-state storage devices

Mohammad Amin Shokrollahi, Luoming Zhang, Yuval Cassuto

A multi-level cell flash memory storage device has cells wherein different charge levels represent different information. The storage device can read stored charge from one or more cells, store a rewrite generation value for a group of a plurality of cells ...

2014

Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design

Giovanni De Micheli, Andreas Peter Burg, Davide Sacchetto, Yusuf Leblebici, Pierre-Emmanuel Julien Marc Gaillardon, Pascal Andreas Meinerzhagen

The total power budget of Ultra-Low Power (ULP) VLSI Systems-on-Chip (SoCs) is often dominated by the leakage power of embedded memories as well as status registers. On the one hand, supply voltage scaling down to the near-threshold (near-VT

Institute of Electrical and Electronics Engineers2014

Scale-Out NUMA

Babak Falsafi, Edouard Bugnion, Boris Robert Grot, Alexandros Daglis, Stanko Novakovic

Emerging datacenter applications operate on vast datasets that are kept in DRAM to minimize latency. The large number of servers needed to accommodate this massive memory footprint requires frequent server-to-server communication in applications such as ke ...

2014