Concept

AI accelerator

Related lectures (15)

IcySoC: Inexact Sub- and Near-Threshold Systems

Covers inexact sub- and near-threshold systems for ultra-low power devices and multi-scale systems engineering.

Explores GPUs' architecture, multithreading, and their role in machine learning, discussing limitations and future trends.

Accelerated Data Management Systems

Explores accelerated data management systems through real-time specialization on heterogeneous hardware and GPU accessing fresh data from CPU memory.

Ultra-Low Power Computing Toolbox

Introduces the IcySoC project, focusing on ultra-low power computing and approximate computing techniques for energy efficiency and performance optimization.

Multi Masters Systems

Explores Multi Masters Systems, discussing architectures with multiple processors, shared memory, mutual exclusion, and hardware accelerators.

Computational Study of Quantum Interaction Phenomena

Delves into computational quantum interaction phenomena in materials using high-performance computing, covering N-particle quantum mechanics, ab initio approaches, and the NOMAD Center of Excellence.

Performance Metrics: Evaluation and Tools

Explores performance metrics, Amdahl's Law implications, means evaluation, challenges in multiprocessor systems, and commercial server software.

Storage Management in SmartDataLake

Explores storage management challenges in transitioning to data lakes, addressing software and hardware heterogeneity, unified storage design, and performance optimization.

Topology Imperfections: Overcoming Hybrid CPU-GPU Analytics

Explores overcoming topology imperfections in analytics through hybrid CPU-GPU architectures and load balancing.

GPU Memory Hierarchy: Optimization

Discusses GPU memory hierarchy and optimization strategies for efficient memory access and execution.

GPU Memory Hierarchy: Optimization

Explores GPU memory hierarchy, CUDA processing flow, optimizations, and parallelism efficiency on GPUs.

GPU Memory Hierarchy and Optimization

Explores GPU memory hierarchy, optimization challenges, and algorithm efficiency.

Numerical Encoding for DNN Accelerators

Explores novel numerical encoding for DNNs, optimizing accuracy and hardware efficiency, and multi-player information advantage.

Instruction Set Extensions: High-Level Synthesis Techniques

Covers instruction set extensions and high-level synthesis techniques for optimizing embedded processors.

High-Level Synthesis: Formally Verified Elastic Circuits

Presents the development of a verified high-level synthesis compiler for elastic circuits.