Instruction cycle

Applied sciences
Computer engineering
Hardware engineering
Microprocessors

About
Privacy
Disclaimer

Graph Chatbot

Related publications (30)

Energy-Aware Processing Platform Exploration for Embedded Biosignal Analysis

Ahmed Yasir Dogan

According to the World Health Organization, lifestyle-related diseases, e.g., cardiovascular diseases are the major cause of mortality worldwide. An accurate and continuous medical supervision is highly required for diagnosis and treatment of such diseases ...

EPFL2013

Reducing OLTP Instruction Misses With Thread Migration

Anastasia Ailamaki, Pinar Tözün

During an instruction miss a processor is unable to fetch instructions. The more frequent instruction misses are the less able a modern processor is to find useful work to do and thus performance suffers. Online transaction processing (OLTP) suffers from h ...

2012

NOC-Out: Microarchitecting a Scale-Out Processor

Babak Falsafi, Boris Robert Grot, Pejman Lotfi Kamran

Scale-out server workloads benefit from many-core processor organizations that enable high throughput thanks to abundant request-level parallelism. A key characteristic of these workloads is the large instruction footprint that exceeds the capacity of priv ...

2012

Low-power processor architecture exploration for online biomedical signal analysis

David Atienza Alonso, Andreas Peter Burg, Luca Benini, Jeremy Hugues-Felix Constantin, Ahmed Yasir Dogan

In this study, the authors explore sequential and parallel processing architectures, utilising a custom ultra-low-power (ULP) processing core, to extend the lifetime of health monitoring systems, where slow biosignal events and highly parallel computations ...

Inst Engineering Technology-Iet2012

Simulation of High-Performance Memory Allocators

David Atienza Alonso, José Luis Risco Martin

This study presents a single-core and a multi-core processor architecture for health monitoring systems where slow biosignal events and highly parallel computations exist. The single-core architecture is composed of a processing core (PC), an instruction m ...

Elsevier2011

Power/Performance Exploration of Single-core and Multi-core Processor Approaches for Biomedical Signal Processing

David Atienza Alonso, Ahmed Yasir Dogan, Andreas Peter Burg, Luca Benini

Springer-Verlag Heidelberg2011

Tight Failure Detection Bounds on Atomic Object Implementations

Rachid Guerraoui

This article determines the weakest failure detectors to implement shared atomic objects in a distributed system with crash-prone processes. We first determine the weakest failure detector for the basic register object. We then use that to determine the we ...

2010

Performance Analysis of the SHA-3 Candidates on Exotic Multi-core Architectures

Joppe Willem Bos, Deian Stefan

The NIST hash function competition to design a new cryptographic hash standard 'SHA-3' is currently one of the hot topics in cryptologic research, its outcome heavily depends on the public evaluation of the remaining 14 candidates. There have been several ...

Springer-Verlag New York, Ms Ingrid Cunningham, 175 Fifth Ave, New York, Ny 10010 Usa2010

Distributed Compressed Sensing for Sensor Networks Using Thresholding

Pierre Vandergheynst, Mohammad Golbabaee

Distributed compressed sensing is the extension of compressed sampling (CS) to sensor networks. The idea is to design a CS joint decoding scheme at a central decoder (base station) that exploits the inter-sensor correlations, in order to recover the whole ...

2009

Improving instruction cache performance in OLTP

Anastasia Ailamaki

Instruction-cache misses account for up to 40%; of execution time in online transaction processing (OLTP) database workloads. In contrast to data cache misses, instruction misses cannot be overlapped with out-of-order execution. Chip design limitations do ...

Association for Computing Machinery2006

Page 2 of 2