Publications related to X86 instruction listings

Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs

Mathias Josef Payer, Mirjana Stojilovic, Shashwat Shrivastava, Ognjen Glamocanin, Jinwei Yao, Nour Ardo

Side-channel disassembly attacks recover CPU instructions from power or electromagnetic side-channel traces measured during code execution. These attacks typically rely on physical access, proximity to the victim device, and high sampling rate measuring in ...

2023

Micro BTB: A High Performance and Storage Efficient Last-Level Branch Target Buffer for Servers

Vishal Gupta

High-performance branch target buffers (BTBs) and the L1I cache are key to high-performance front-end. Modern branch predictors are highly accurate, but with an increase in code footprint in modern-day server workloads, BTB and L1I misses are still frequen ...

ASSOC COMPUTING MACHINERY2022

Synthesis of Flexible Accelerators for Early Adoption of Ring-LWE Post-quantum Cryptography

Francesco Regazzoni, Subhadeep Banik, Hamid Nejatollahi

The advent of the quantum computer makes current public-key infrastructure insecure. Cryptography community is addressing this problem by designing, efficiently implementing, and evaluating novel public-key algorithms capable of withstanding quantum comput ...

ASSOC COMPUTING MACHINERY2020

SoK: Shining Light on Shadow Stacks

Mathias Josef Payer, Xiangyu Zhang

Control-Flow Hijacking attacks are the dominant attack vector against C/C++ programs. Control-Flow Integrity (CFI) solutions mitigate these attacks on the forward edge, i.e., indirect calls through function pointers and virtual calls. Protecting the backwa ...

IEEE COMPUTER SOC2019

The effects of haptic-virtual reality game therapy on brain-motor coordination for children with hemiplegia: A pilot study

Mohamed Bouri

Children with hemiplegia have movements' difficulties especially in their upper limbs, these difficulties occur due to the loss of the communication between the brain and the affected side of the body. In this study, visual, audio, and tactile stimulation ...

IEEE2017

Microarchitectural Low-Power Design Techniques for Embedded Microprocessors

Jeremy Hugues-Felix Constantin

With the omnipresence of embedded processing in all forms of electronics today, there is a strong trend towards wireless, battery-powered, portable embedded systems which have to operate under stringent energy constraints. Consequently, low power consumpti ...

EPFL2016

DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment

Andreas Peter Burg, Adam Shmuel Teman, Thomas Christoph Müller, Andrea Bonetti, Jeremy Hugues-Felix Constantin, Lorenz Flavio Schmid

This paper presents DynOR, a 32-bit 6-stage OpenRISC microprocessor with dynamic clock adjustment. To alleviate the issue of unused dynamic timing margins, the clock period of the processor is adjusted on a cycle-by-cycle level, based on the instruction ty ...

Ieee2016

Exploiting Dynamic Timing Margins in Microprocessors for Frequency-Over-Scaling with Instruction-Based Clock Adjustment

Andreas Peter Burg, Georgios Karakonstantis, Jeremy Hugues-Felix Constantin, Anupam Chattopadhyay

Static timing analysis provides the basis for setting the clock period of a microprocessor core, based on its worst-case critical path. However, depending on the design, this critical path is not always excited and therefore dynamic timing margins exist th ...

2015

Way Stealing: A Unified Data Cache and Architecturally Visible Storage for Instruction Set Extensions

Edoardo Charbon, Paolo Ienne, Ties Jan Henderikus Kluter, Philip Brisk

Way Stealing is a simple architectural modification to a cache-based processor that increases the data bandwidth to and from application-specific instruction set extensions (ISEs), which increase performance and reduce energy consumption. Way Stealing offe ...

Institute of Electrical and Electronics Engineers2014

STREX: Boosting Instruction Cache Reuse in OLTP Workloads Through Stratified Transaction Execution

Anastasia Ailamaki, Pinar Tözün, Xin Tong

Online transaction processing (OLTP) workload performance suffers from instruction stalls; the instruction footprint of a typical transaction exceeds by far the capacity of an L1 cache, leading to ongoing cache thrashing. Several proposed techniques remove ...

2013

Optically-Clocked Instruction Set Extensions for High Efficiency Embedded Processors

Edoardo Charbon, Ties Jan Henderikus Kluter, Claudio Favi, Christian Mester

We propose a technique to localize computation in Instruction Set Extensions (ISEs) that are clocked at very high speed with respect to the processor. In order to save power, data to and from Custom Instruction Units (CIUs) is synchronized via an optical s ...

2012

Bringing Virtualization to the x86 Architecture with the Original VMware Workstation

Edouard Bugnion

This article describes the historical context, technical challenges, and main implementation techniques used by VMware Workstation to bring virtualization to the x86 architecture in 1999. Although virtual machine monitors (VMMs) had been around for decades ...

Association for Computing Machinery2012

Efficient Hashing Using the AES Instruction Set

Joppe Willem Bos, Martijn Stam, Onur Özen

In this work, we provide a software benchmark for a large range of 256-bit blockcipher-based hash functions. We instantiate the underlying blockcipher with AES, which allows us to exploit the recent AES instruction set (AESNI). Since AES itself only output ...

Springer Berlin Heidelberg2011

System for generating computer processor

A method and apparatus to produce a net list of gates and Flip-Flops for one algorithm in order to find the best compromise between power consumption, speed and silicon surface by using a two step process. First the algorithm is written for a processor tha ...

2010

Architecture of a Real-Time Platform Independant GPS L1 Software Receiver

Personal digital assistants or mobile phones applications are not anymore restricted to multimedia or wireless communications, but have been extended to handle Global Positioning System (GPS) functionalities. Consequently, the growing market of GPS capable ...

EPFL2010

Performance Analysis of the SHA-3 Candidates on Exotic Multi-core Architectures

Joppe Willem Bos, Deian Stefan

The NIST hash function competition to design a new cryptographic hash standard 'SHA-3' is currently one of the hot topics in cryptologic research, its outcome heavily depends on the public evaluation of the remaining 14 candidates. There have been several ...

Springer-Verlag New York, Ms Ingrid Cunningham, 175 Fifth Ave, New York, Ny 10010 Usa2010

Fast, Nearly Optimal ISE Identification with I/O Serialization through Maximal Clique Enumeration

Paolo Ienne, Philip Brisk, Ajay Kumar Verma

The last decade has witnessed the emergence of the application-specific instruction-set processor (ASIP) as a viable platform for embedded systems. Extensible ASIPs allow the user to augment a base processor with instruction set extensions (ISEs) that exec ...

2010

Deep-submicron embedded processor architectures for high-performance, low-cost and low-power

Sylvain Aguirre

Because the market has an insatiable appetite for new functionality, performance is becoming an increasingly important factor. The telecommunication and network domains are especially touched by this phenomenon but they are not the only ones. For instance, ...

EPFL2007

Improving instruction cache performance in OLTP

Anastasia Ailamaki

Instruction-cache misses account for up to 40%; of execution time in online transaction processing (OLTP) database workloads. In contrast to data cache misses, instruction misses cannot be overlapped with out-of-order execution. Chip design limitations do ...

Association for Computing Machinery2006