Publications related to Green thread

Secure Interface Design Leveraging Hardware/Software Support

Computer systems rely heavily on abstraction to manage the exponential growth of complexity across hardware and software. Due to practical considerations of compatibility between components of these complex systems across generations, developers have favou ...

EPFL2024

Thread-Placement Learning

Rachid Guerraoui, Vasileios Trigonakis, Karolos Antoniadis

In a non-uniform memory access machine, the placement of software threads to hardware cores can have a significant effect on the performance of concurrent applications. Detecting the best possible placement for each application is a necessity for thread sc ...

IEEE COMPUTER SOC2020

Task scheduling for highly concurrent analytical and transaction workloads

Anastasia Ailamaki, Iraklis Psaroudakis

Systems and method for a task scheduler with dynamic adjustment of concurrency levels and task granularity are disclosed for improved execution of highly concurrent analytical and transactional systems. The task scheduler can avoid both over commitment and ...

2020

A Shared-Memory Parallel Implementation of the RePlAce Global Cell Placer

Mirjana Stojilovic, Philip Brisk, Frédéric Gessler

RePlAce is a state-of-the-art prototype of a flat, analytic, and nonlinear global cell placement algorithm, which models a placement instance as an electrostatic system with positively charged objects. It can handle large-scale standard-cell and mixed-cell ...

IEEE2020

Stretch: Balancing QoS and Throughput for Colocated Server Workloads on SMT Cores

Boris Robert Grot, Siddharth Gupta

In a drive to maximize resource utilization, today's datacenters are moving to colocation of latency-sensitive and batch workloads on the same server. State-of-the-art deployments, such as those at Google, colocate such diverse workloads even on a single S ...

IEEE2019

Improving Main-memory Database System Performance through Cooperative Multitasking

Georgios Psaropoulos

Database systems access memory either sequentially or randomly. Contrary to sequential access and despite the extensive efforts of computer architects, compiler writers, and system builders, random access to data larger than the processor cache has been s ...

EPFL2019

Deterministic Parallel Routing for FPGAs based on Galois Parallel Execution Model

Mirjana Stojilovic, Philip Brisk

This paper describes a deterministic and parallel implementation of the VPR routability-driven router for FPGAs. We considered two parallefization strategies: (1) routing multiple nets in parallel; and (2) routing one net at a time, while parallelizing the ...

IEEE2018

Theory and Practice of Coroutines with Snapshots

Aleksandar Prokopec, Fengyun Liu

While event-driven programming is a widespread model for asynchronous computing, its inherent control flow fragmentation makes event-driven programs notoriously difficult to understand and maintain. Coroutines are a general control flow construct that can ...

2018

A Dynamically Reconfigurable Platform for High-Performance and Low-Power On-Board Processing

Paolo Ienne, Andrea Guerrieri, Sahand Kashani

FPGAs (Field Programmable Gate Array) are an attractive technology for high-speed data processing in space missions due to their unbeatable flexibility and best performance-to-power ratio in comparison to software. However FPGAs suffer from 3 major drawbac ...

IEEE2018

Interleaving with Coroutines: A Practical Approach for Robust Index Joins

Anastasia Ailamaki, Georgios Psaropoulos

Index join performance is determined by the efficiency of the lookup operation on the involved index. Although database indexes are highly optimized to leverage processor caches, main memory accesses inevitably increase lookup runtime when the index outsiz ...

VLDB Endowment Inc.2017

A Scala Library for Testing Student Assignments on Concurrent Programming

Mikaël Mayer, Ravichandhran Kandhadai Madhavan

We present a lightweight library for testing concurrent Scala programs by systematically exploring multiple interleavings between user-specified operations on shared objects. Our library is targeted at beginners of concurrent programming in Scala, runs on ...

Assoc Computing Machinery2016

Unlocking Energy

Rachid Guerraoui, Babak Falsafi, Vasileios Trigonakis, Javier Picorel Obando

Locks are a natural place for improving the energy efficiency of software systems. First, concurrent systems are mainstream and when their threads synchronize, they typically do it with locks. Second, locks are well-defined abstractions, hence changing the ...

Usenix Assoc2016

Automated Classification of Data Races Under Both Strong and Weak Memory Models

George Candea, Cristian Zamfir, Baris Can Cengiz Kasikci

Data races are one of the main causes of concurrency problems in multithreaded programs. Whether all data races are bad, or some are harmful and others are harmless, is still the subject of vigorous scientific debate [Narayanasamy et al. 2007; Boehm 2012]. ...

Assoc Computing Machinery2015

Language Support for Distributed Functional Programming

Heather Christine Klug

Software development has taken a fundamental turn. Software today has gone from simple, closed programs running on a single machine, to massively open programs, patching together user experiences byway of responses received via hundreds of network requests ...

EPFL2015

Leveraging Hardware Message Passing for Efficient Thread Synchronization

André Schiper, Thomas Ropars, Darko Petrovic

As the level of parallelism in manycore processors keeps increasing, providing efficient mechanisms for thread synchronization in concurrent programs is becoming a major concern. On cache-coherent shared-memory processors, synchronization efficiency is ult ...

2014

Leveraging Hardware Message Passing for Efficient Thread Synchronization

André Schiper, Thomas Ropars, Darko Petrovic

As the level of parallelism in manycore processors keeps increasing, providing efficient mechanisms for thread synchronization in concurrent programs is becoming a major concern. On cache-coherent shared-memory processors, synchronization efficiency is ult ...

Assoc Computing Machinery2014

ATraPos: Adaptive Transaction Processing on Hardware Islands

Anastasia Ailamaki, Pinar Tözün, Danica Porobic, Erietta Liarou

Nowadays, high-performance transaction processing applications increasingly run on multisocket multicore servers. Such architectures exhibit non-uniform memory access latency as well as non-uniform thread communication costs. Unfortunately, traditional sha ...

2014

Parallel algorithms and efficient implementation techniques for finite element approximations

Radu Popescu

In this thesis we study the efficient implementation of the finite element method for the numerical solution of partial differential equations (PDE) on modern parallel computer archi- tectures, such as Cray and IBM supercomputers. The domain-decomposition ...

EPFL2013

Execution Synthesis: A Technique for Automating the Debugging of Software

Cristian Zamfir

Debugging real systems is hard, requires deep knowledge of the target code, and is time-consuming. Bug reports rarely provide sufficient information for debugging, thus forcing developers to turn into detectives searching for an explanation of how the prog ...

EPFL2013

Achieving high-throughput State Machine Replication in multi-core systems

André Schiper, Nuno Filipe de Sousa Santos

The traditional architecture used by implementations of Replicated State Machines (RSM) does not fully exploit modern multi-core CPUs. This is increasingly the limiting factor in their performance, because network speeds are increasing much faster than the ...

Ieee2013