Publications related to C to HDL

Highly Parallel RTL Simulation

Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL. As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and ...

EPFL2024

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

Sahand Kashani

The demise of Moore's Law and Dennard scaling has resulted in diminishing performance gains for general-purpose processors, and so has prompted a surge in academic and commercial interest for hardware accelerators. Specialized hardware has already redefine ...

EPFL2023

Finding a Needle in the Haystack of Hardened Interconnect Patterns

Paolo Ienne, Grace Zgheib, Stefan Nikolic

Circuits naturally exhibit recurring patterns of local interconnect. Hardening those patterns when designing Field Programmable Gate Array (FPGA) clusters can both eliminate slow programmable connections from the critical path and remove the need for trans ...

IEEE2019

Pyramic: Full Stack Open Microphone Array Architecture And Dataset

René Beuchat, Robin Scheibler, Corentin Ferry

In this paper we introduce an open source and reproducible microphone array hardware design and an anechoic dataset recorded with this array. The Pyramic array has 48 microphones spread onto six identical modules connected to an FPGA-ARM combo. The arrange ...

IEEE2018

System Level simulation framework for the ASICs development of a novel particle physics detector

Yusuf Leblebici, Alessandro Caratelli, Davide Ceresa, Simone Scarfì

The simulation of the passage of particles through matter using Monte Carlo methods is broadly used in the development of particle detectors for high energy physics experiments. To develop the readout electronics for the Compact Muon Solenoid (CMS) experim ...

IEEE2018

High level synthesis of Smith-Waterman dataflow implementations

Marco Mattavelli, Simone Casale Brunet, Endri Bezati

The paper presents the results of design explorations for the implementation of the Smith-Waterman (S-W) algorithm executing DNA and protein sequences alignment. Both design explorations studies and the corresponding FPGA implementations are obtained by wr ...

2017

Hardware-in-the-Loop Validation of an FPGA-Based Real-Time Simulator for Power Electronics Applications

Mario Paolone, Farhad Rachidi-Haeri, Reza Razzaghi

This paper presents the hardware-in-the-loop (HIL) validation of a proposed FPGA-based real-time simulator for power electronics applications. The proposed FPGA-based real-time simulation platform integrates the Modified Nodal Analysis (MNA) method, Fixed ...

ipst.org2015

High-level dataflow design of signal processing systems for reconfigurable and multicore heterogeneous platforms

Marco Mattavelli, Endri Bezati, Ghislain Roquier, Richard Thavot

The potential computational power of today multicore processors has drastically improved compared to the single processor architecture. Since the trend of increasing the processor frequency is almost over, the competition for increased performance has move ...

Springer Heidelberg2014

Coarse Grain Clock Gating Of Streaming Applications In Programmable Logic Implementations

Marco Mattavelli, Endri Bezati, Simone Casale Brunet

Streaming applications describe a broad class of computing algorithms in areas such as signal processing, media coding and compression, cryptography, video analytics, network touting and packet processing and many others. For many of these applications, pr ...

Ieee2014

A general purpose FPGA-based real-time simulator for power systems applications

Mario Paolone, Farhad Rachidi-Haeri, Reza Razzaghi

This paper presents an FPGA-based (field programmable gate array) real-time digital simulator for power systems and power electronics applications. The proposed approach integrates the Modified Nodal Analysis (MNA) method, the Fixed Admittance Matrix Nodal ...

IEEE Power Engineering Society2013

Biconditional BDD: A Novel Canonical BDD for Logic Synthesis targeting XOR-rich Functions

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù

We present a novel class of decision diagrams, called Biconditional Binary Decision Diagrams (BBDDs), that enable efficient logic synthesis for XOR-rich functions. BBDDs are binary decision diagrams where the Shannon’s expansion is replaced by the bicondit ...

2013

High-Level Synthesis of Dataflow Programs for Signal Processing Systems

Marco Mattavelli, Endri Bezati

The growing complexity of signal processing algorithms and platforms poses significant challenges to design methods and implementation tools. High-level dataflow programs, such as those in MPEG's RVC-CAL language, provide abstraction and the opportunity fo ...

2013

Shortening design time through multiplatform simulations with a portable OpenCL golden-model: the LDPC decoder case

Andreas Peter Burg, Paolo Ienne, Georgios Karakonstantis, David Novo Bruna, Gabriel Falcao Paiva Fernandes, Madhura Purnaprajna

Hardware designers and engineers typically need to explore a multi-parametric design space in order to ﬁnd the best conﬁguration for their designs using simulations that can take weeks to months to complete. For example, designers of special purpose chips ...

2012

Formal Analysis of SystemC Designs in Process Algebra

Hossein Hojjat

SystemC is an IEEE standard system-level language used in hardware/software co-design and has been widely adopted in the industry. This paper describes a formal approach to verifying SystemC designs by providing a mapping to the process algebra mCRL2. Our ...

2011

Dataflow Programming for Systems Design Space Exploration for Multicore Platforms

Christophe Lucarz

Nowadays processing systems are asked to support increasing complex and demanding high-performance applications, especially in the signal processing and video processing domains. The design of these systems are becoming extremely challenging because of sev ...

EPFL2011

Optimization Methodologies for Complex FPGA-based Signal Processing Systems with CAL

Marco Mattavelli, Christophe Lucarz, Anatoly Prihozhy, Ab Al Hadi Bin Ab Rahman, Hossam Amer

Signal processing designs are becoming increasingly complex with demands for more advanced algorithms. Designers are now seeking high-level tools and methodology to help manage complexity and increase productivity. Recently, CAL dataflow language has been ...

2011

SystemC-Based Modeling of Embedded Heterogeneous Systems

Alain Vachoux, Torsten Mähne

SystemC is emerging as a de-facto standard for digital system design. Since embedded systems include more and more heterogeneous components (e.g., analog/RF front-ends, processor cores, embedded software, digital hardware, sensors, actuators), the need for ...

2008

Dataflow/Actor-Oriented language for the design of complex signal processing systems

Marco Mattavelli, Christophe Lucarz, Ghislain Roquier

Signal processing algorithms become more and more complex and the algorithm architecture adaptation and design processes cannot any longer rely only on the intuition of the designers to build efficient systems. Specific tools and methods are needed to cope ...

2008

Diseño de redes en chip de propósito específico con información de rutado físico

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Srinivasan Murali, Federico Angiolini, Roman Hermida Correa

The equivalent English title: "Design of Custom Networks-on-Chip with Physical Layout Information" Abstract translated into English: Due to the growing demand of communication between processors and memory devices in Systems-on-Chip (SoCs), recently the ne ...

2006

Routing Aware Switch Hardware Customization for Networks on Chips

Giovanni De Micheli, Srinivasan Murali

Networks on Chip (NoC) has been proposed as a scalable and reusable solution for interconnecting the ever- growing number of processor/memory cores on a single silicon die. As the hardware complexity of a NoC is significant, methods for designing a NoC wit ...

2006