Basic PipeliningExplores basic pipelining in circuits, improving speed and throughput with multiple operations performed simultaneously.
Finite Automata: BasicsIntroduces the basics of finite automata, including deterministic and non-deterministic types, regular expressions, and acceptance criteria.
Keylock in VHDL and on FPGACovers the design of a KeyLock system in VHDL, focusing on the FSM implementation for key validation and LED indication.
Universal Source CodingCovers the Lempel-Ziv universal coding algorithm and invertible finite state machines in information theory.
FSM Design and SynthesisCovers the design and synthesis of Finite State Machines, including completeness, consistency, ghost states, and transition tables.
FSM Design and SynthesisCovers the design and synthesis of Finite State Machines, emphasizing completeness, consistency, and ghost states.
Formally Verified Chisel DesignsExplores formally verifying Chisel designs using SMT solvers and covers examples like delayed assertions and proofs by induction.
