Formally Verified Chisel DesignsExplores formally verifying Chisel designs using SMT solvers and covers examples like delayed assertions and proofs by induction.
From Algorithms to ArchitecturesExplores the transition from algorithms to hardware architectures in digital system design, covering isomorphic architectures, VHDL implementation, and hardware efficiency metrics.
Introduction au VHDLCovers VHDL basic concepts, program structure, objects, types, operators, literals, and arrays.
VHDL for SynthesisCovers basic VHDL constructs for RTL design, including arithmetic, multiplexers, registers, and instantiation.
Keylock in VHDL and on FPGACovers the design of a KeyLock system in VHDL, focusing on the FSM implementation for key validation and LED indication.