Semicustom RTL Design: Frontend with Synthesis

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Semicustom RTL Design: Design Flow and Standard Cells

Explores the RTL design flow, chip-level integration, standard cells, and static timing analysis in VLSI design.

Semicustom RTL Design: Backend

Explores the backend design flow in semicustom ASIC design, covering layout, clock tree generation, and tapeout preparation.

Hardware Description Languages

Explores the history and significance of Hardware Description Languages in automating design processes and describing parallel hardware.

How we design chips: The Digital VLSI Design Flow

Explores the principles and methodologies for designing integrated circuits, covering design flows, VLSI styles, abstraction levels, and the semiconductor ecosystem.

Logical Effort: Fundamentals of VLSI Design

Covers the Logical Effort method for optimizing logic delay and gate sizing impact.

Synchronous Digital Circuits: Principles and Design

Covers principles of synchronous RTL design, custom digital circuits, Y-Diagram visualization, signal classes, and hierarchy management.

Fundamentals of VLSI Design

Covers the fundamentals of VLSI design, focusing on circuit optimization and complex system composition.

Simulation-Based Verification

Explores simulation-based verification in VLSI systems using compiled-code and event-driven algorithms.

Introduction to Advanced VLSI Design

Covers Advanced VLSI Design concepts, including Full Custom Design and Parallel Prefix Adder.

Static Timing Analysis

Explores static timing analysis in digital system design, covering setup and hold time requirements, critical paths, and timing conditions.

Basic Synchronous Digital Circuits and RTL Design

Covers pulse generation, edge detection, common design mistakes, and clock/reset signals in logic circuits.

Field Programmable Gate Arrays (FPGAs)

Covers the basic principles and architecture of Field Programmable Gate Arrays (FPGAs) and their implementation options for digital circuits.

PVT Variations, Uncertainty, and Monte-Carlo Simulations

Explores the impact of PVT variations, uncertainties in IC design, worst-case design paradigms, and the importance of Monte-Carlo simulations.

VHDL for Synthesis

Covers basic VHDL constructs for RTL design, including arithmetic, multiplexers, registers, and instantiation.

Digital Logic Circuits: CMOS and Verilog Design

Discusses digital logic circuits, CMOS technology, and Verilog for circuit design.

Hardware Verification using High-Level Design Languages

Explores challenges in hardware verification, clear specifications, speculation harm, and cycle-precise semantics.

Virtual Machine Access: Setup and Design Environment

Covers the setup and access to virtual machines for IC design practical exercises.

Physical Design Basics

Introduces the basics of physical design in VLSI chip design, emphasizing layout features, power supply wiring, and gate layout optimization.

FPGA Programming with Speedgoat: Real-Time Signal Processing

Focuses on implementing a square function generator using Speedgoat FPGA technology and real-time signal processing techniques.

High-Level Synthesis: Formally Verified Elastic Circuits

Presents the development of a verified high-level synthesis compiler for elastic circuits.

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