Lectures related to Simulation-Based Verification

Hardware Description Languages

Explores the history and significance of Hardware Description Languages in automating design processes and describing parallel hardware.

Simulation and Modeling in VLSI Systems

Explores simulation techniques and fault simulation procedures in VLSI systems.

Semicustom RTL Design: Frontend with Synthesis

Covers the fundamentals of VLSI design, focusing on the semi-custom design flow.

FPGA Programming with Speedgoat: Real-Time Signal Processing

Focuses on implementing a square function generator using Speedgoat FPGA technology and real-time signal processing techniques.

VHDL for Simulation & Testbenches

Explores VHDL for simulation, debugging, time modeling, event-based simulation, and testbench creation in digital system design.

Hardware Verification using High-Level Design Languages

Explores challenges in hardware verification, clear specifications, speculation harm, and cycle-precise semantics.

Optimization and Simulation: Introduction to Simulation

Introduces state-of-the-art methods in optimization and simulation, covering topics like statistical analysis, variance reduction, and simulation projects.

Semicustom RTL Design: Design Flow and Standard Cells

Explores the RTL design flow, chip-level integration, standard cells, and static timing analysis in VLSI design.

Generating a CLK Generator (PLL) IP in Vivado

Covers the process of generating a Clock Generator (PLL) IP in Vivado using the Clocking Wizard tool.

Synchronous Digital Circuits: Principles and Design

Covers principles of synchronous RTL design, custom digital circuits, Y-Diagram visualization, signal classes, and hierarchy management.

Discrete Event Simulation

Covers discrete event simulation using digital circuits, base components, complex components, and simulation implementation.

Field Programmable Gate Arrays (FPGAs)

Covers the basic principles and architecture of Field Programmable Gate Arrays (FPGAs) and their implementation options for digital circuits.

High-Level Synthesis: Formally Verified Elastic Circuits

Presents the development of a verified high-level synthesis compiler for elastic circuits.

Instruction Set Extensions: High-Level Synthesis Techniques

Covers instruction set extensions and high-level synthesis techniques for optimizing embedded processors.

VHDL for Synthesis

Covers basic VHDL constructs for RTL design, including arithmetic, multiplexers, registers, and instantiation.

How we design chips: The Digital VLSI Design Flow

Explores the principles and methodologies for designing integrated circuits, covering design flows, VLSI styles, abstraction levels, and the semiconductor ecosystem.

Compiler verification: Challenges and Benefits

Explores the challenges and benefits of compiler verification, emphasizing the importance of verifying compilers for critical software.

Simulation & Optimization: Poisson Process & Random Numbers

Explores simulation pitfalls, random numbers, discrete & continuous distributions, and Monte-Carlo integration.

Molecular Transistors: Design and Simulation

Explores molecular transistors for logic computation, design, simulation, and fabrication, emphasizing interconnect parasitics and device performance.

Test Environment Setup

Covers the setup of a test environment for VLSI design.