Publications by Ilhan Hatirnaz

Early Wire Characterization for Predictable Network-on-Chip Global Interconnects

Yusuf Leblebici, Stéphane Badel, Ilhan Hatirnaz, Giovanni De Micheli, David Atienza Alonso, Srinivasan Murali

This work envisions a common design methodology, applicable for every interconnect level and based on early wire characterization, to provide a faster convergence to a feasible and robust design. We claim that such a novel design methodology is vital for u ...

ACM Press New York, NY, US2007

Predictable System Interconnects Through an Accurate Early Wire Characterization

Yusuf Leblebici, Stéphane Badel, Ilhan Hatirnaz

2007

Via-Programmable Expanded Universal Logic Gate in MCML for Structured ASIC Applications: Circuit Design

Yusuf Leblebici, Stéphane Badel, Ilhan Hatirnaz

This paper presents a via-programmable expanded universal logic gate in MOS current-mode logic which can implement any 3-input Boolean function, and a significant subset of 4-input and 5-input functions. The universal logic gate is programmed with the firs ...

2006

Implementation of Structured ASIC Fabric Using Via-Programmable Differential MCML Cells

Yusuf Leblebici, Stéphane Badel, Ilhan Hatirnaz

This paper presents a regular layout fabric made of via-programmable MCML universal logic cells for structured ASIC applications and the associated design flow. The proposed structured ASIC fabric offers very high noise immunity due to the differential ope ...

2006

Via-programmable Structured ASIC Fabric Based on MCML Cells (poster)

Yusuf Leblebici, Stéphane Badel, Ilhan Hatirnaz

2006

A new interconnect-centric design methodology for high-speed standard cells with crosstalk immunity

Ilhan Hatirnaz

One of the biggest challenges that are facing the Very Large Scale Integrated Circuits (VLSI) technologies today is the significant performance gap (3× to 9×) between full custom circuits and Application Specific Integrated Circuits (ASICs) designed in the ...

EPFL2006

Semi-Automated Design of a MOS Current Mode Logic Standard Cell Library from Generic Components

Yusuf Leblebici, Stéphane Badel, Ilhan Hatirnaz

This paper describes the design and semi-automated generation of a MOS current-mode logic standard cell library. A set of generic components implementing a wide range of combinational and sequential functions is proposed. The layout of the generic componen ...

2005

Towards a Unified Top-Down Design Flow for Fully-Differential Logic Blocks with Improved Speed and Noise Immunity

Yusuf Leblebici, Stéphane Badel, Ilhan Hatirnaz

A new top-down design flow (RTL-to-GDSII) is proposed for achieving high-performance and noiseimmune designs consisting of differential logic blocks. The differential building blocks are based on the currentmode logic (CML), which offers true differentiali ...

2005