Publications by Pascal Andreas Meinerzhagen

Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement

Pascal Andreas Meinerzhagen, Luca Benini, Andreas Peter Burg, Adam Shmuel Teman

Embedded memory remains a major bottleneck in current integrated circuit design in terms of silicon area, power dissipation, and performance; however, static random access memories (SRAMs) are almost exclusively supplied by a small number of vendors throug ...

Association for Computing Machinery2016

Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS

Pascal Andreas Meinerzhagen, Andreas Peter Burg, Oskar Andersson

In this study, design considerations for ultra low voltage (ULV) standard-cell based memories (SCM) are presented. Trade-offs for area cost, leakage power, access time, and access energy are discussed and realized using different read logic styles, latch a ...

Institute of Electrical and Electronics Engineers2016

Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications

Pascal Andreas Meinerzhagen, Andreas Peter Burg, Adam Shmuel Teman, Robert Giterman

Logic compatible gain cell (GC) embedded DRAM (eDRAM) arrays are considered an alternative to SRAM due to their small size, non-ratioed operation, low static leakage, and 2-port functionality. However, traditional GC-eDRAM implementations require boosted c ...

Ieee-Inst Electrical Electronics Engineers Inc2016

A Process Compensated Gain Cell Embedded-DRAM for Ultra-Low-Power Variation-Aware Design

Pascal Andreas Meinerzhagen, Andreas Peter Burg, Adam Shmuel Teman, Robert Giterman

Gain cell embedded DRAM (GC-eDRAM) is a high-density alternative to SRAM for ultra-low-power systems. However, due to its dynamic nature, GC-eDRAM requires power-hungry refresh cycles to ensure data retention. Traditional design approaches dictate configur ...

Ieee2016

Refresh-Free Dynamic Standard-Cell Based Memories: Application to a QC-LDPC Decoder

Pascal Andreas Meinerzhagen, Andreas Peter Burg, Georgios Karakonstantis, Andrea Bonetti

The area and power consumption of low-density parity check (LDPC) decoders are typically dominated by embedded memories. To alleviate such high memory costs, this paper exploits the fact that all internal memories of a LDPC decoder are frequently updated w ...

2015

Energy versus Data Integrity Trade-Offs in Embedded High-Density Logic Compatible Dynamic Memories

Pascal Andreas Meinerzhagen, Andreas Peter Burg, Georgios Karakonstantis, Adam Shmuel Teman, Robert Giterman

Current variation aware design methodologies, tuned for worst-case scenarios, are becoming increasingly pessimistic from the perspective of power and performance. A good example of such pessimism is setting the refresh rate of DRAMs according to the worst- ...

2015

Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design

Yusuf Leblebici, Pascal Andreas Meinerzhagen, Giovanni De Micheli, Davide Sacchetto, Andreas Peter Burg, Pierre-Emmanuel Julien Marc Gaillardon

The total power budget of Ultra-Low Power (ULP) VLSI Systems-on-Chip (SoCs) is often dominated by the leakage power of embedded memories as well as status registers. On the one hand, supply voltage scaling down to the near-threshold (near-VT

Institute of Electrical and Electronics Engineers2014

4T Gain-Cell with internal-feedback for ultra-low retention power at scaled CMOS nodes

Pascal Andreas Meinerzhagen, Andreas Peter Burg, Adam Shmuel Teman, Robert Giterman

Gain-Cell embedded DRAM (GC-eDRAM) has recently been recognized as a possible alternative to traditional SRAM. While GC-eDRAM inherently provides high-density, low-leakage, low-voltage, and 2-ported operation, its limited retention time requires periodic, ...

IEEE2014

Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM

Pascal Andreas Meinerzhagen, Andreas Peter Burg, Adam Shmuel Teman, Robert Giterman

Gain cells have recently been shown to be a viable alternative to static random access memory in low-power applications due to their low leakage currents and high density. The primary component of power consumption in these arrays is the dynamic power cons ...

Institute of Electrical and Electronics Engineers2014

Novel Approaches Toward Area- and Energy-Efficient Embedded Memories

Pascal Andreas Meinerzhagen

EPFL2014

Impact of body biasing on the retention time of gain-cell memories

Pascal Andreas Meinerzhagen, Andreas Peter Burg, Adam Shmuel Teman

Gain-cell-based embedded dynamic random-access memory (DRAMs) are a potential high-density alternative to mainstream static random-access memory (SRAM). However, the limited data retention time of these dynamic bitcells results in the need for power-consum ...

2013

Exploration of Sub-VT and Near-VT 2T Gain-Cell Memories for Ultra-Low Power Applications under Technology Scaling

Pascal Andreas Meinerzhagen, Andreas Peter Burg, Adam Shmuel Teman, Robert Giterman

Ultra-low power applications often require several kb of embedded memory and are typically operated at the lowest possible operating voltage (VDD) to minimize both dynamic and static power consumption. Embedded memories can easily dominate the overall sili ...

2013

FireBird: PowerPC e200 Based SoC for High Temperature Operation

Thomas Maeder, Yusuf Leblebici, Pascal Andreas Meinerzhagen, Radisav Cojbasic, Andreas Peter Burg, Conor Joseph Slater, Ömer Cogal, Carl Christian Sten Dominic Senning

PowerPC Architecture microcontrollers are commonly used in embedded applications. In this work we present FireBird, the first PowerPC based SoC for reliable operation beyond 200C. It is a significant challenge to design SoCs for reliable operation at high ...

2013

A ReRAM-Based Non-Volatile Flip-Flop with Sub-VT Read and CMOS Voltage-Compatible Write

Pascal Andreas Meinerzhagen, Giovanni De Micheli, Davide Sacchetto, Andreas Peter Burg, Pierre-Emmanuel Julien Marc Gaillardon

The total power budget of Ultra-Low Power (ULP) VLSI Systems-on-Chip (SoCs) is often dominated by the leakage power of embedded memories and pipeline registers, which typically cannot be power-gated during sleep periods as they need to retain data and prog ...

2013

Replica Bit-Line Technique for Embedded Multilevel Gain-Cell DRAM

Pascal Andreas Meinerzhagen, Andreas Peter Burg, Muhammad Umer Khalid

Multilevel gain-cell DRAMs are interesting to improve the area-efficiency of modern fault-tolerant systems-on-chip implemented in deep-submicron CMOS technologies. This paper addresses the problem of long access times in such multilevel gain-cell DRAMs, wh ...

Ieee2012

A Sub-VT 2T Gain-Cell Memory for Biomedical Applications

Pascal Andreas Meinerzhagen, Andreas Peter Burg, Adam Shmuel Teman

All state-of-the-art subthreshold (sub-VT) memories are based on static bitcells, while the feasibility and limitations of dynamic bitcells operated in the sub-VT regime have not been studied yet. For the first time ever, we examine the sub-VT operation of ...

2012

TamaRISC-CS: An Ultra-Low-Power Application-Specific Processor for Compressed Sensing

Pascal Andreas Meinerzhagen, David Atienza Alonso, Ahmed Yasir Dogan, Andreas Peter Burg, Jeremy Hugues-Felix Constantin, Oskar Andersson

Compressed sensing (CS) is a universal technique for the compression of sparse signals. CS has been widely used in sensing platforms where portable, autonomous devices have to operate for long periods of time with limited energy resources. Therefore, an ul ...

2012

Two-Port Low-Power Gain-Cell Storage Array: Voltage Scaling and Retention Time

Pascal Andreas Meinerzhagen, Andreas Peter Burg, Rashid Iqbal

The impact of supply voltage scaling on the retention time of a 2-transistor (2T) gain-cell (GC) storage array is investigated, in order to enable low-power/low-voltage data storage. The retention time can be increased when scaling down the supply voltage ...

2012

Standard-Cell Based Memories (SCMs): from Sub-VT to Error-Resilient Systems

Pascal Andreas Meinerzhagen, Andreas Peter Burg

Embedded memories consume an increasingly dominant part of the overall area and power of a large variety of systems-on-chip [ITRS’09]: 1) biomedical implants and wireless sensor networks require robust memories operating in the sub-VT domain; 2) many handh ...

2012

A 500 fW/bit 14 fJ/bit-access 4kb Standard-Cell Based Sub-VT Memory in 65nm CMOS

Pascal Andreas Meinerzhagen, Andreas Peter Burg, Oskar Andersson

Ultra-low power (ULP) biomedical implants and sensor nodes typically require small memories of a few kb, while previous work on reliable subthreshold (sub-Vt) memories targets several hundreds of kb. Standard-cell based memories (SCMs) are a straightforwar ...

2012