Publications by Pietro Buccella

SPICE Modeling of Photoelectric Effects in Silicon With Generalized Devices

Jean-Michel Sallese, Pietro Buccella, Camillo Stefanucci, Chiara Rossi

Modeling photoelectric effects in semiconductors with electrical simulators is demonstrated in typical 1-D and 2-D architectures. The concept is based on a coarse meshing of the semiconductor with the so-called generalized lumped devices, where equivalent ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2018

Modeling Surface Recombination with Enhanced Devices Network for Optoelectronics

Jean-Michel Sallese, Pietro Buccella, Camillo Stefanucci, Chiara Rossi

We present a lumped devices network approach to simulate surface recombination effects in optoelectronics devices. The network is composed of generalized lumped devices where the excess carrier concentrations and gradients are mapped on electrical quantiti ...

IEEE2018

Simulation, Analysis, and Verification of Substrate Currents for Layout Optimization of Smart Power ICs

Maher Kayal, Jean-Michel Sallese, Pietro Buccella, Camillo Stefanucci

Today circuit failures in Smart Power ICs due to substrate couplings are partially addressed during the circuit design phase. The state-of-the-art guidelines for the optimization of parasitic couplings provide mainly qualitative rules, which are difficult ...

Institute of Electrical and Electronics Engineers2016

Analysis of Substrate Currents Propagation in HVCMOS technology

Maher Kayal, Jean-Michel Sallese, Pietro Buccella, Camillo Stefanucci

This work reports the results of a layout-aware substrate modeling methodology for HVCMOS technologies. The model relies on the extraction of parasitic substrate network to simulate with circuit software parasitic lateral NPN bipolar transistors with multi ...

IEEE2016

Methodology for 3-D Substrate Network Extraction for SPICE Simulation of Parasitic Currents in Smart Power ICs

Maher Kayal, Jean-Michel Sallese, Pietro Buccella, Camillo Stefanucci

A 3-D simulation of substrate currents is crucial to analyze parasitic coupling effects due to minority carrier injection in smart power ICs. In this paper, a substrate parasitic extraction methodology is introduced by dividing the IC layout into elementar ...

Ieee-Inst Electrical Electronics Engineers Inc2016

Active Guard Ring Characterization for Smart Power ICs

Maher Kayal, Jean-Michel Sallese, Pietro Buccella, Camillo Stefanucci

This paper shows SPICE simulation results of active guard ring structures which are typically employed in Smart Power ICs. Active guard rings act as barriers limiting the flow of minority carriers injected into the substrate toward sensitive circuits. The ...

Ieee2016

Substrate Current Optimization in Smart Power ICs

Pietro Buccella

Safety requirements for modern automotive electronics call for more and more robust power integrated circuits. The mixed-signal IC design flow alone is often no longer capable of tracking possible design failures in complex Smart Power integrated circuits ...

EPFL2016

Spice Simulation of Passive Protection in Smart Power ICs

Maher Kayal, Jean-Michel Sallese, Pietro Buccella, Camillo Stefanucci

When designing in Smart Power technologies, TCAD simulations are mandatory to design effective passive protections against parasitic couplings due to minority carriers. The objective of this paper is to propose a spice-based approach to characterize electr ...

Ieee2015

Modeling Parasitic Vertical PNP in HVCMOS

Maher Kayal, Jean-Michel Sallese, Pietro Buccella, Camillo Stefanucci

High voltage CMOS active devices inherently have a parasitic vertical bipolar transistor. The parasitic PNP structure can be activated during high-power switching operation causing a potential shift of the substrate. In this work a spice-modeling approach ...

IEEE2015

Modeling Minority Carriers Related Capacitive Effects for Transient Substrate Currents in Smart Power ICs

Maher Kayal, Jean-Michel Sallese, Pietro Buccella, Camillo Stefanucci

This paper presents an extended model for transient and ac circuit-level simulation of minority carriers propagation through the substrate of smart power integrated circuits (ICs). A p-n junction and a diffusion resistor with capacitive components are prop ...

Institute of Electrical and Electronics Engineers2015

Spice-compatible modeling of high injection and propagation of minority carriers in the substrate of Smart Power ICs

Maher Kayal, Jean-Michel Sallese, Pietro Buccella, Camillo Stefanucci

Classical substrate noise analysis considers the silicon resistivity of an integrated circuit only as doping dependent besides neglecting diffusion currents as well. In power circuits minority carriers are injected into the substrate and propagate by drift ...

Elsevier2015

Impact of enhanced contact doping on minority carriers diffusion currents

Maher Kayal, Jean-Michel Sallese, Pietro Buccella, Camillo Stefanucci

Minority carriers diffusion currents are particularly important in parasitic substrate couplings of Smart Power ICs. In CMOS technologies the P-substrate potential is imposed by P+ contacts and N-wells by N+ highly doped implantations. The doping concentra ...

IEEE2014

Optimization Strategy of Numerical Simulations Applied to EPFL Substrate Model

Maher Kayal, Jean-Michel Sallese, Pietro Buccella, Camillo Stefanucci

A new methodology for modeling minority carriers diffusion in Smart Power ICs substrate using standard circuit simulators has been proposed by EPFL. For this purpose, a parasitic substrate network consisting of lumped elements is extracted from the circuit ...

Ieee2014

Spice Simulation of Substrate Minority Carriers Propagation with Equivalent Electrical Circuit

Maher Kayal, Jean-Michel Sallese, Pietro Buccella, Camillo Stefanucci

This paper presents an equivalent electrical circuit for one dimensional substrate minority carriers spice simulation. The electrical circuit parameters are extracted from substrate meshing applying the finite difference method. This model is derived from ...

Ieee2014