Skip to main content

Search

Show all results for

Home

Person

Seyed Armin Tajalli

About
Privacy
Disclaimer

Copyright © 2026 EPFL, all rights reserved

Graph Chatbot

About this result

This page is automatically generated and may contain information that is not correct, complete, up-to-date, or relevant to your search query. The same applies to every other page on this website. Please make sure to verify the information with EPFL's official sources.

Related units (1)

Integrated Neurotechnologies Laboratory

EPFL
STI
IEM
INL

Related publications (48)

Please note that this is not a complete list of this person’s publications. It includes only semantically relevant works. For a full list, please refer to Infoscience.

ISI Sensitivity of PAM Signaling for Very High-Speed Short-Reach Copper Links

Yusuf Leblebici, Seyed Armin Tajalli, Ayça Akkaya, Firat Çelik

This paper presents a comparative study, analyzing the potentials of pulse amplitude modulation (PAM) for implementing next generation high-speed copper wireline links. This comparative study analyzes the sensitivities of PAM2, PAM4 and PAM8 to inter-symbo ...

IEEE2019

A Review on Quantum Computing: From Qubits to Front-end Electronics and Cryogenic MOSFET Physics

Jean-Michel Sallese, Seyed Armin Tajalli, Farzan Jazaeri, Arnout Lodewijk M Beckers

Quantum computing (QC) has already entered the industrial landscape and several multinational corporations have initiated their own research efforts. So far, many of these efforts have been focusing on superconducting qubits, whose industrial progress is c ...

IEEE2019

JESD204B Compliant 12.5 Gb/s LVDS and SST Transmitters in 28 nm FD-SOI CMOS

Yusuf Leblebici, Seyed Armin Tajalli, Andreas Peter Burg, Ayça Akkaya, Firat Çelik

JESD204B compliant low-voltage differential signaling (LVDS), and source-series-terminated (SST) transmitters in 28 nm FD-SOI CMOS technology are presented with 1.1 pJ/bit and 1.7 pJ/bit at 12.5 Gb/s, respectively. An external 6.25 GHz single-ended clock, ...

IEEE2019