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Luca Benini

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Related publications (77)

Application of FPGA Emulation to SoC Floorplan and Packaging Exploration

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Pablo Garcia del Valle, Roman Hermida Correa

New tendencies in the consumer electronics market present Multi-Processor Systems-On-Chip (MPSoCs) as a promising solution for meeting the processing demands of upcoming generations of user applications. MPSoCs are complex to design, as they must execute m ...

2007

Multi-Processor Operating System Emulation Framework with Thermal Feedback for Systems-on-Chip

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Pablo Garcia del Valle, Francisco Javier Rincon Vallejos

Multi-Processor System-On-Chip (MPSoC) can provide the performance levels required by high-end embedded applications. However, they do so at the price of an increasing power density, which may lead to thermal runaway if coupled with low-cost packaging and ...

2007

Bringing NoCs to 65nm

Giovanni De Micheli, David Atienza Alonso, Federico Angiolini, Luca Benini, Srinivasan Murali

Very deep submicron process technologies are ideal application fields for NoCs, which offer a promising solution to the scalability problem. This article sheds light on the benefits and challenges of Noc-Based interconnect design in nanometer CMOS. The aut ...

2007

An Application-Specific Design Methodology for On-chip Crossbar Generation

Giovanni De Micheli, Luca Benini, Srinivasan Murali

Designing a power-efficient interconnection architec- ture for MultiProcessor Systems-on-Chips (MPSoCs) satisfying the application performance constraints is a nontrivial task. In order to meet the tight time-to-market constraints and to effec- tively hand ...

Institute of Electrical and Electronics Engineers2007

Synthesis of Predictable Networks-on-Chip Based Interconnect Architectures for Chip Multi-Processors

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Srinivasan Murali

Today, chip multiprocessors (CMPs) that accommodate multiple processor cores on the same chip have become a reality. As the communication complexity of such multicore systems is rapidly increasing, designing an interconnect architecture with predictable be ...

2007

Timing-Error-Tolerant Network-on-Chip Design Methodology

Giovanni De Micheli, Federico Angiolini, Luca Benini, Srinivasan Murali

With technology scaling, the wire delay as a fraction of the total delay is increasing, and the communication architecture is becoming a major bottleneck for system performance in systems on chip (SoCs). A communication-centric design paradigm, networks on ...

2007

Improving the Fault Tolerance of Nanometric PLA Designs

Giovanni De Micheli, David Atienza Alonso, Mohamed Haykel Ben Jamaa, Federico Angiolini, Luca Benini

Several alternative building blocks have been proposed to replace planar transistors, among which a prominent spot belongs to nanometric laments such as Silicon NanoWires (SiNWs) and Carbon NanoTubes (CNTs). However, chips leveraging these nanoscale struct ...

2007

A Multi-Path Routing Strategy with Guaranteed In-order Packet Delivery and Fault Tolerance for Networks on Chips

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Srinivasan Murali

In this work we present a multi-path routing strategy that guarantees in-order packet delivery for Networks on Chips (NoCs). We present a design methodology that uses the routing strategy to optimally spread the traffic in the NoC to minimize the network b ...

2006

A Complete Multi-Processor System-on-Chip FPGA-Based Emulation Framework

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Pablo Garcia del Valle

With the growing complexity in consumer embedded products and the improvements in process technology, Multi-Processor System-On-Chip (MPSoC) architectures have become widespread. These new systems are very complex to design as they must execute multiple co ...

2006

Designing Application-Specific Networks on Chips with Floorplan Information

Giovanni De Micheli, David Atienza Alonso, Federico Angiolini, Luca Benini, Srinivasan Murali

With increasing communication demands of processor and memory cores in Systems on Chips (SoCs), scalable Networks on Chips (NoCs) are needed to interconnect the cores. For the use of NoCs to be feasible in today’s industrial designs, a custom-tailored, app ...

2006

Diseño de redes en chip de propósito específico con información de rutado físico

Giovanni De Micheli, David Atienza Alonso, Federico Angiolini, Luca Benini, Srinivasan Murali, Roman Hermida Correa

The equivalent English title: "Design of Custom Networks-on-Chip with Physical Layout Information" Abstract translated into English: Due to the growing demand of communication between processors and memory devices in Systems-on-Chip (SoCs), recently the ne ...

2006

Bioimaging and Functional Genomics

Giovanni De Micheli, Luca Benini

For better understanding of genetic mechanisms underlying clinical observations, it is interesting to determine which genes and clinical traits are interrelated. In the last few years a consistent amount of research in genomics has been done concerning cor ...

2006

Reliability Support for On-chip Memories Using Networks-on-Chips

Giovanni De Micheli, David Atienza Alonso, Federico Angiolini, Luca Benini, Srinivasan Murali

As the geometries of the transistors reach the physical limits of operation, one of the main design challenges of Systems-on-Chips (SoCs) will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. ...

2006

Comparison of a Timing-Error Tolerant Scheme with a Traditional Re-transmission Mechanism for Networks on Chips

Giovanni De Micheli, David Atienza Alonso, Federico Angiolini, Luca Benini, Srinivasan Murali

On-chip wires are becoming unreliable as the effect of various noise sources increases with technology scaling. This leads to unpredictable timing delay variations on the interconnect wires. There is a significant need to mitigate the effect of parasitics ...

2006

Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips

Giovanni De Micheli, David Atienza Alonso, Federico Angiolini, Luca Benini, Srinivasan Murali

Networks on Chip (NoC) has emerged as the paradigm for designing scalable communication architecture for Systems on Chips (SoCs). Avoiding the conditions that can lead to deadlocks in the network is critical for using NoCs in real designs. Methods that can ...

2006

Architectural Exploration of MPSoC Designs Based on an FPGA Emulation Framework

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Pablo Garcia del Valle

2006

A Novel Approach for Network on Chip Emulation

Giovanni De Micheli, Nicolas Genko, David Atienza Alonso, Luca Benini, Roman Hermida Correa

Current Systems-On-Chip execute applications that demand extensive parallel processing. Networks-On-Chip (NoC) provide a structured way of realizing interconnections on silicon, and obviate the limitations of bus-based solutions. NoCs can have regular or a ...

2005

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