Publications by Alessandro Cevrero

A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET

Yusuf Leblebici, Alessandro Cevrero, Andreas Peter Burg, Gain Kim, Lukas Kull, Thomas Toifl, Cosimo Aprile, Ilter Ozkaya

This article introduces a wireline receiver (RX) data-path employing discrete multi-tone (DMT) modulation for communicating over electrical links. The DMT RX incorporates a fully digital equalization data-path, with a synthesized and automatically placed a ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

A 4.8pJ/b 6Gb/s ADC-Based PAM-4 Wireline Receiver Data -Path with Cyclic Prefix in 14nm FinFET

Yusuf Leblebici, Alessandro Cevrero, Andreas Peter Burg, Gain Kim, Lukas Kull, Thomas Toifl, Cosimo Aprile, Ilter Ozkaya

This work presents an ADC-bascd receiver (RX) data-path for frame-based PAM-4 modulation with a cyclic prefix (CP). Similar to discrete multi-tone (DMT) modulation, a frame of PAM-4 symbols arc protected from the channel delay spread by the CP taps. A PAM- ...

IEEE2019

A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET

Yusuf Leblebici, Alessandro Cevrero, Andreas Peter Burg, Gain Kim, Lukas Kull, Thomas Toifl, Cosimo Aprile, Ilter Ozkaya

IEEE2019

4x40 Gb/s 2 pJ/bit Optical RX with 8ns Power-on and CDR-Lock Time in 14nm CMOS

Alessandro Cevrero, Thomas Toifl, Ilter Ozkaya

We report a low-power 4-channel NRZ optical RX including a digital burst-mode CDR measured up to 40Gb/s/lane in 14nm CMOS. The RX, designed for 850nm VCSEL based optical links, can wake-up and achieve phase-lock in 8ns at BER

IEEE2018

A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET

Yusuf Leblebici, Alessandro Cevrero, Lukas Kull, Thomas Toifl, Ilter Ozkaya

2018

A 112Gb/s 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS

Alessandro Cevrero, Lukas Kull, Thomas Toifl, Ilter Ozkaya

IEEE2018

A 56Gb/s Burst-Mode NRZ Optical Receiver with 6.8ns Power-On and CDR-Lock Time for Adaptive Optical Links in 14nm FinFET CMOS

Yusuf Leblebici, Alessandro Cevrero, Lukas Kull, Thomas Toifl, Ilter Ozkaya

IEEE2018

Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver

Yusuf Leblebici, Alessandro Cevrero, Gain Kim, Lukas Kull, Thomas Toifl, Cosimo Aprile, Ilter Ozkaya

This paper presents a parallel implementation technique of digital equalizer for high-speed wireline serial link receiver (RX). In wireline RX, inter-symbol interference (ISI) is mitigated by continuous-time linear equalizer, and the remaining ISI is cance ...

2018

A 24-to-72GS/s 8b Time-Interleaved SAR ADC with 2.0-to-3.3pJ/conversion and > 30dB SNDR at Nyquist in 14nm CMOS FinFET

Alessandro Cevrero, Lukas Kull, Thomas Toifl, Ilter Ozkaya

IEEE2018

An Eight lanes 7Gb/s/pin Source Synchronous Single-Ended RX with Equalization and Far-End Crosstalk Cancellation for Backplane Channels

Yusuf Leblebici, Alessandro Cevrero, Lukas Kull, Volkan Cevher, Thomas Toifl, Cosimo Aprile

This paper presents a versatile crosstalk cancellation scheme for single-ended multi-lane backplane links. System-level investigations show that a scheme, which combines analog filters and decision-feedback crosstalk compensation on the receiver (RX) side ...

2018

A 64Gb/s 1.4pJ/b NRZ Optical-Receiver Data-Path in 14nm CMOS FinFET

Yusuf Leblebici, Alessandro Cevrero, Lukas Kull, Thomas Toifl, Ilter Ozkaya

This work describes a NRZ receiver data-path fabricated in 14nm bulk FinFET technology and characterized in an 850nm VCSEL based optical link up to 64Gb/s. It achieves 1.42pJ/bit energy efficiency while recovering PRBS-7 data (BER< 10-12) modulated by a VC ...

Ieee2017

A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET

Yusuf Leblebici, Alessandro Cevrero, Lukas Kull, Thomas Toifl, Ilter Ozkaya

A 64-Gb/s high-sensitivity non-return to zero receiver (RX) data-path is demonstrated in the 14-nm-bulk FinFET CMOS technology. To achieve high sensitivity, the RX incorporates a transimpedance amplifier whose gain and bandwidth are co-optimized with a 1-t ...

Institute of Electrical and Electronics Engineers2017

A 60 Gb/s 1.9 pJ/bit NRZ Optical-Receiver with Low Latency Digital CDR in 14nm CMOS FinFET

Yusuf Leblebici, Alessandro Cevrero, Lukas Kull, Thomas Toifl, Ilter Ozkaya

This work reports a low power implementation of a 60Gb/s NRZ optical receiver (RX) in 14nm bulk CMOS finFET featuring a first-order digital CDR with high jitter tolerance (JTOL). The design includes a single phase-rotator (PR) with low complexity control l ...

2017

Impact of Data Serialization over TSVs on Routing Congestion in 3D-Stacked Multi-Core Processors

Yusuf Leblebici, Giovanni De Micheli, Alessandro Cevrero, Giulia Beanato

3D integration can alleviate routing congestion, reducing the wirelength and improving performances. Nevertheless, each TSV still occupies non-negligible silicon area: as the number of TSV increases, their effect on the chip routing is detrimental. The red ...

Elsevier2016

Design and Analysis of Jitter-Aware Low-Power and High-Speed TSV Links for 3D ICs

Yusuf Leblebici, Giovanni De Micheli, Alessandro Cevrero, Giulia Beanato, Kiarash Gharibdoust

This paper presents a circuit-level design and analysis of high-data-rate 3D serial vertical links which exploit the high bandwidth provided by TSV technology. As most of the existing TSVs consume a large amount of die area, the serial configuration can sa ...

Elsevier2016

A 5.9mW/Gb/s 7Gb/s/pin 8-Lane Single-Ended RX with Crosstalk Cancellation Scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS

Yusuf Leblebici, Alessandro Cevrero, Lukas Kull, Volkan Cevher, Thomas Toifl, Cosimo Aprile, Ilter Ozkaya

This work reports an 8-lane single-ended RX featuring compact and low power far-end crosstalk (FEXT) cancellation circuits. The RX data-path consists of a cross continuous-time linear equalizer (XCTLE) to remove FEXT by nearest aggressors within the channe ...

2015

Low Power 3D Serial TSV Link for High Bandwidth Cross-Chip Communication

Yusuf Leblebici, Giovanni De Micheli, Alessandro Cevrero, Giulia Beanato

3D-ICs based on TSV technology provide high bandwidth inter-chip connections. The drawback is that most of the existing TSVs consume a large amount of silicon real estate. We present circuit-level design and analysis of area efficient, low power, high-data ...

2014

Generalized programmable counter arrays

Philip Brisk, Alessandro Cevrero, Hadi Parandeh Afshar

A Generalized Programmable Counter Array (GPCA) is a reconfigurable multi-operand adder, which can be reprogrammed to sum a plurality of operands of arbitrary size. The GPCA is configured to compress the input words down to two operands using parallel coun ...

2014

Heterogeneous integration of ReRAM crossbars in a CMOS foundry chip

Yusuf Leblebici, Giovanni De Micheli, Alessandro Cevrero, Davide Sacchetto, Jury Sandrini, Pierre-Emmanuel Julien Marc Gaillardon, Tugba Demirci

In this paper, we present a heterogeneous integration of ReRAMs with standard CMOS technology by post-processing the Back-End-of-the-Line (BEOL) of fully finished CMOS chips. ...

2014

Advanced CMOS Circuits for Multi-Gb/s Links and 3D I/O Based on Through Silicon Via Technology

Alessandro Cevrero

EPFL2014