Publications by Hu Xu | EPFL Graph Search

Timing Uncertainty in 3-D Clock Trees due to Process Variations and Power Supply Noise

Giovanni De Micheli, Hu Xu, Vasileios Pavlidis, Wayne Burleson, Xifan Tang

Clock distribution networks are affected by different sources of variations. The resulting clock uncertainty significantly affects the frequency of a circuit. To support this analysis, a statistical model of skitter, which consists of clock skew and jitter ...

Institute of Electrical and Electronics Engineers2013

Effects of Process Variations on 3-D Global Clock Distribution Networks

Giovanni De Micheli, Hu Xu, Vasileios Pavlidis

In three-dimensional (3D) integrated circuits, the effect of process variations on clock skew differs from 2D circuits. The combined effect of inter-die and intra-die process variations on the design of 3D clock distribution networks is considered in this ...

Assoc Computing Machinery2012

Modeling and Design Techniques for 3-D ICs under Process, Voltage, and Temperature Variations

Hu Xu

Three-dimensional (3-D) integration is a promising solution to further enhance the density and performance of modern integrated circuits (ICs). In 3-D ICs, multiple dies (tiers or planes) are vertically stacked. These dies can be designed and fabricated se ...

EPFL2012

Enhanced Wafer Matching Heuristics for 3-D ICs

Giovanni De Micheli, Hu Xu, Vasileios Pavlidis

Ieee2012

The Combined Effect of Process Variations and Power Supply Noise on Clock Skew and Jitter

Giovanni De Micheli, Hu Xu, Vasileios Pavlidis, Wayne Burleson

In modern VLSI circuits, a large number of clock buffers are inserted in clock distribution networks, which are significantly affected by process and power supply noise variations. The combined effect of process variations and power supply noise on clock s ...

Ieee2012

Analytical Heat Transfer Model for Thermal Through-Silicon Vias

Giovanni De Micheli, Hu Xu, Vasileios Pavlidis

Thermal issues are one of the primary challenges in 3-D integrated circuits. Thermal through-silicon vias (TTSVs) are considered an effective means to reduce the temperature of 3-D ICs. The effect of the physical and technological parameters of TTSVs on th ...

2011

Skew Variability in 3-D ICs with Multiple Clock Domains

Giovanni De Micheli, Hu Xu, Vasileios Pavlidis

The effect of process variations on the clock skew in three dimensional (3-D) circuits with multiple clock domains is investigated. In 3-D ICs, the combined effect of inter-die and intra-die process variations should be considered in the design of clock di ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2011

Process-induced skew variation for scaled 2-D and 3-D ICs

Giovanni De Micheli, Hu Xu, Vasileios Pavlidis

Technology scaling and three-dimensional integration are two design paradigms that offer high device density. Process variations affect these design paradigms in different ways. The effect of process variations on clock skew for a 2-D circuit implemented a ...

ACM Press2010

Synchronization and Power Integrity Issues in 3-D ICs

Giovanni De Micheli, Ioannis Tsioutsios, Hu Xu, Vasileios Pavlidis

Several challenges should be resolved for three dimensional integration to evolve to a mainstream technology. Among these challenges, the issues of synchronization and power integrity become predominant due to the multiple planes and the heterogeneity of 3 ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2010

Repeater Insertion for Two-Terminal Nets in Three-Dimensional Integrated Circuits

Giovanni De Micheli, Hu Xu, Vasileios Pavlidis

A new approach for inserting repeaters in 3-D interconnects is proposed. The allocation of repeaters along an interplane interconnect is iteratively determined. The proposed approach is compared with two other techniques based on conventional methods used ...

2009