Publications by Giulia Beanato

Impact of Data Serialization over TSVs on Routing Congestion in 3D-Stacked Multi-Core Processors

Yusuf Leblebici, Giovanni De Micheli, Alessandro Cevrero, Giulia Beanato

3D integration can alleviate routing congestion, reducing the wirelength and improving performances. Nevertheless, each TSV still occupies non-negligible silicon area: as the number of TSV increases, their effect on the chip routing is detrimental. The red ...

Elsevier2016

Design and Analysis of Jitter-Aware Low-Power and High-Speed TSV Links for 3D ICs

Yusuf Leblebici, Giovanni De Micheli, Alessandro Cevrero, Giulia Beanato, Kiarash Gharibdoust

This paper presents a circuit-level design and analysis of high-data-rate 3D serial vertical links which exploit the high bandwidth provided by TSV technology. As most of the existing TSVs consume a large amount of die area, the serial configuration can sa ...

Elsevier2016

Low Power 3D Serial TSV Link for High Bandwidth Cross-Chip Communication

Yusuf Leblebici, Giovanni De Micheli, Alessandro Cevrero, Giulia Beanato

3D-ICs based on TSV technology provide high bandwidth inter-chip connections. The drawback is that most of the existing TSVs consume a large amount of silicon real estate. We present circuit-level design and analysis of area efficient, low power, high-data ...

2014

Speed/Power/Area Trade-offs for High Speed Inter Layer Data Transmission in 3D Stacked ICs

Giulia Beanato

EPFL2014

3D-MMC: A Modular 3D Multi-Core Architecture with Efficient Resource Pooling

Yusuf Leblebici, Ayse Kivilcim Coskun, Panagiotis Athanasopoulos, Alessandro Cevrero, Giulia Beanato

2013

Towards Cost Effective Multi-Core Processor Platforms Using 3-D Stacking Technology

Yusuf Leblebici, Panagiotis Athanasopoulos, Alessandro Cevrero, Giulia Beanato

A novel modular, cost e ffective 3D multi-processor architecture is presented. Auto-configurable and independently testable identical dies are stacked exploiting Through-Silicon-Vias (TSV) technology, allowing to target different market segments by selecti ...

2012

Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology

Yusuf Leblebici, Panagiotis Athanasopoulos, Michail Zervas, Alessandro Cevrero, Yüksel Temiz, Giulia Beanato, Paolo Giovannini

An innovative modular 3-D stacked multi-processor architecture is presented. The platform is composed of completely identical stacked dies connected together by through-silicon-vias (TSVs). Each die features four 32-bit embedded processors and associated m ...

2012

A 3D Stacked Multi-Core Processor Platform with Improved Testability

Yusuf Leblebici, Panagiotis Athanasopoulos, Alessandro Cevrero, Giulia Beanato, Paolo Giovannini

2012