Publications by Ivan Beretta | EPFL Graph Search

Parallelizing the Chambolle Algorithm for Performance Optimized Mapping on FPGA devices

David Atienza Alonso, Abdulkadir Akin, Ivan Beretta, Alessandro Antonio Nacci

The performance and the efficiency of recent computing platforms have been deeply influenced by the widespread adoption of hardware accelerators, such as Graphics Processing Units (GPUs) or Field Programmable Gate Arrays (FPGAs), which are often employed t ...

Assoc Computing Machinery2016

Efficient Hardware Design Of Iterative Stencil Loops

David Atienza Alonso, Ivan Beretta, Alessandro Antonio Nacci

A large number of algorithms for multidimensional signals processing and scientific computation come in the form of iterative stencil loops (ISLs), whose data dependencies span across multiple iterations. Because of their complex inner structure, automatic ...

Ieee-Inst Electrical Electronics Engineers Inc2016

Hardware/Software Approach for Code Synchronization in Low-Power Multi-Core Sensor Nodes

David Atienza Alonso, Ruben Braojos Lopez, Ivan Beretta, Giovanni Ansaloni

Latest embedded bio-signal analysis applications, targeting low-power Wireless Body Sensor Nodes (WBSNs), present conflicting requirements. On one hand, bio-signal analysis applications are continuously increasing their demand for high computing capabiliti ...

IEEE/ACM Press2014

Early Classification of Pathological Heartbeats on Wireless Body Sensor Nodes

David Atienza Alonso, Ruben Braojos Lopez, Ivan Beretta, Giovanni Ansaloni

Smart Wireless Body Sensor Nodes (WBSNs) are a novel class of unobtrusive, battery-powered devices allowing the continuous monitoring and real-time interpretation of a subject's bio-signals, such as the electrocardiogram (ECG). These low-power platforms, w ...

MDPI2014

A Mapping-Scheduling Algorithm for Hardware Acceleration on Reconfigurable Platforms

David Atienza Alonso, Ivan Beretta, Juan Antonio Clemente Barreira

Reconfigurable platforms are a promising technology that offers an interesting trade-off between flexibility and performance, which many recent embedded system applications demand, especially in fields such as multimedia processing. These applications typi ...

Assoc Computing Machinery2014

Design Methodologies for Application-Oriented Embedded Systems Under Variable Performance/Constraints Tradeoffs

Ivan Beretta

EPFL2014

A High-Level Synthesis Flow for the Implementation of Iterative Stencil Loop Algorithms on FPGA Devices

David Atienza Alonso, Ivan Beretta, Alessandro Antonio Nacci

The automatic generation of hardware implementations for a given algorithm is generally a difficult task, especially when data dependencies span across multiple iterations such as in iterative stencil loops (ISLs). In this paper, we introduce an automatic ...

IEEE/ACM Press2013

Design Methods for Parallel Hardware Implementation of Multimedia Iterative Algorithms

David Atienza Alonso, Ivan Beretta, Alessandro Antonio Nacci

Traditionally, parallel implementations of multimedia algorithms are carried out manually, since the automation of this task is very difficult due to the complex dependencies that generally exist between different elements of the data set. Moreover, there ...

Institute of Electrical and Electronics Engineers2013

Design Exploration of Energy-Performance Trade-offs for Wireless Sensor Networks

David Atienza Alonso, Francisco Javier Rincon Vallejos, Nadia Khaled, Ivan Beretta

Wireless sensor networks (WNSs) are gradually evolving from a promising technology to a well-established reality in a large set of different domains. In order to fulfill the requirements of the specific scenario, a WSN must provide the right tradeoffs betw ...

IEEE2012

Knowledge-based design space exploration of wireless sensor networks

David Atienza Alonso, Ivan Beretta

The complexity of Wireless Sensor Networks (WSNs) has been constantly increasing over the last decade, and the necessity of efficient CAD tools has been growing accordingly. In fact, the size of the design space of a WSN has become large, and an exploratio ...

ACM Press2012

Model-Based Design for Wireless Body Sensor Network Nodes

David Atienza Alonso, Francisco Javier Rincon Vallejos, Nadia Khaled, Ivan Beretta

Wireless body sensor networks (WBSNs) are a rising technology that allows constant and unobtrusive monitoring of the vital signals of a patient. The configuration of a WBSN node proves to be critical in order to maximize its lifetime, while meeting the pre ...

IEEE Press2012

A High–Performance Parallel Implementation of the Chambolle Algorithm

David Atienza Alonso, Abdulkadir Akin, Ivan Beretta, Alessandro Antonio Nacci

The determination of the optical flow is a central problem in image processing, as it allows to describe how an image changes over time by means of a numerical vector field. The estimation of the optical flow is however a very complex problem, which has be ...

ACM and IEEE Press2011

Island-Based Adaptable Embedded System Design

David Atienza Alonso, Ivan Beretta

Nowadays, hardware devices are meant to host the execution of many complex, multi-core applications, whose functional and non-functional requirements vary according to the specific working domain. In this work, we propose a design methodology that combines ...

Institute of Electrical and Electronics Engineers2011

A Mapping Flow for Dynamically Reconfigurable Multi-Core System-on-Chip Design

David Atienza Alonso, Ivan Beretta

Nowadays, multi-core Systems-on-Chip (SoCs) are typically required to execute multiple complex applications, which demand a large set of heterogeneous hardware cores with different sizes. In this context, the popularity of dynamically reconfigurable platfo ...

Institute of Electrical and Electronics Engineers2011

A Hybrid Mapping-Scheduling Technique for Dynamically Reconfigurable Hardware

David Atienza Alonso, Ivan Beretta

Reconfigurable computing is a promising technology that offers an interesting trade-off between flexibility and performance, which many recent multi-core embedded system applications demand. In order to achieve these objectives, it is necessary to optimize ...

ACM and IEEE Press2011

Run-time Mapping of Applications on FPGA-based Reconfigurable Systems

David Atienza Alonso, Ivan Beretta

The role of Field-Programmable Gate Arrays (FPGAs) in System-on-Chip (SoC) design considerably increased in the last few years. Their established importance is due to the large amount of hardware resources they offer, as well as to their increasing perform ...

IEEE Press2010

Run-Time Mapping for Dynamically-Added Applications in Reconfigurable Embedded Systems

David Atienza Alonso, Ivan Beretta

The increasing popularity of multi-core System-on-Chip platforms introduces new challenges, both in terms of hardware platforms and design methodologies. Dynamic reconfiguration can be exploited to increase the flexibility of the system and to implement mu ...

IEEE Press2009