Publications by Mustafa Kilic | EPFL Graph Search

High Speed SAR ADC Architectures in 28nm FDSOI CMOS

The demand on high speed Analog to Digital Converters (ADCs) has increased considerably the last years. From communications circuit to high speed oscilloscopes, Giga Samples per second (GS/s) ADCs are requested. With the scaling of the CMOS technology, des ...

EPFL2019

Generalization of Referenceless Timing Mismatch Calibration Methods for Time-Interleaved ADCs

Yusuf Leblebici, Mustafa Kilic, Arda Uran

Calibration of time-interleaved analog-to-digital converters is a problem whose necessity and complexity increase with the number of interleaved channels. In this study, we develop a generic representation of the referenceless timing mismatch calibration s ...

IEEE2018

A Pipelined Speed Enhancement Technique for CDAC-Threshold Configuring SAR ADC

Yusuf Leblebici, Mustafa Kilic

In this paper, a novel SAR ADC architecture enabling very high speed operation is presented. Based on a hybrid capacitive DAC-threshold configuring scheme, the proposed architecture performs conversions in two-stages, similarly to pipelined ADCs. An additi ...

2018

A hybrid CDAC-threshold configuring SAR ADC in 28nm FDSOI CMOS

Yusuf Leblebici, Mustafa Kilic, Themistoklis Mavrogordatos

2018

A Row-Column Accessed Dynamic Element Matching DAC Architecture for SAR ADCs

Yusuf Leblebici, Mustafa Kilic, Selman Ergünay

Capacitor mismatch in high resolution Successive Approximation Register (SAR) Analog to Digital Converters (ADCs) causes non-linearity effects that reduce the Spurious-Free Dynamic Range (SFDR). This paper presents a novel dynamic element matching (DEM) te ...

IEEE2018

A DAC Assisted Speed Enhancement Technique for High Resolution SAR ADC

Yusuf Leblebici, Mustafa Kilic

In this paper, a technique aiming at enhancing the conversion speed of asynchronous high resolution SAR ADCs is presented. In conventional SAR ADCs, the capacitive DAC size is growing exponentially with the converter resolution. The settling time of the MS ...

2017

A Hybrid CDAC-Threshold Configuring SAR ADC in 28nm FDSOI CMOS

Yusuf Leblebici, Mustafa Kilic, Themistoklis Mavrogordatos

In this paper, a 9-bit 1.3 GS/s single channel SAR ADC is presented. In conventional SAR ADCs, the capacitive DAC size grows exponentially with respect to converter resolution. This results in both signal bandwidth and conversion speed reduction. The propo ...

2017

An Implantable High-Voltage Cortical Stimulator for Post-stroke Rehabilitation Enhancement with High-Current Driving Capacity

Alexandre Schmid, Mustafa Kilic

This paper presents a high-voltage, high-current implantable cortical stimulation integrated circuit aiming at supporting rehabilitation of patients suffering from stroke. In this context, a large area of the motor cortex needs to be stimulated, requiring ...

2015

Column-Separated Compressive Sampling Scheme for Low Power CMOS Image Sensors

Alexandre Schmid, Yusuf Leblebici, Pierre Vandergheynst, Mahdad Hosseini Kamal, Nikola Katic, Mustafa Kilic

A novel compressive sampling scheme suitable for highly scalable hardware implementations is presented. The scheme utilizes an identical pseudo-random sequence for every image column, therefore reducing in-pixel hardware complexity and allowing measurement ...

IEEE2013

Power-Efficient CMOS Image Acquisition System based on Compressive Sampling

Alexandre Schmid, Yusuf Leblebici, Pierre Vandergheynst, Mahdad Hosseini Kamal, Nikola Katic, Mustafa Kilic

A novel compressive sampling scheme suitable for highly scalable hardware implementations is presented. The prototype design is implemented in a 0.18um standard CMOS technology and utilizes compressed acquisition to boost the overall power efficiency. Spec ...

IEEE2013