Mattia Cacciotti

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Related publications (4)

Exploiting Errors for Efficiency: A Survey from Circuits to Applications

Damien Zufferey, Babak Falsafi, Sasa Misailovic, Eva Darulova, Dorde Jevdic, Alexandros Daglis, Mattia Cacciotti

When a computational task tolerates a relaxation of its specification or when an algorithm tolerates the effects of noise in its execution, hardware, system software, and programming language compilers or their runtime systems can trade deviations from cor ...

ASSOC COMPUTING MACHINERY2020

Hardware Acceleration of HDR-Image Tone Mapping on an FPGA-CPU Platform Through High-Level Synthesis

Christian Enz, Vincent Frédéric Camus, Mattia Cacciotti, Jérémy Lucien Maurice Schlachter, Alessandro Pezzotta

In this paper, the hardware acceleration of a tone-mapping algorithm for High-Dynamic-Range image processing is presented. Starting from the C++ source code, High-Level Synthesis has been performed using Xilinx SDSoC for a Xilinx Zynq SoC device. After an ...

IEEE2018

Design of Approximate Circuits by Fabrication of False Timing Paths: The Carry Cut-Back Adder

Christian Enz, Vincent Frédéric Camus, Mattia Cacciotti, Jérémy Lucien Maurice Schlachter

This paper introduces a novel method for designing approximate circuits by fabricating and exploiting false timing paths, i.e. critical paths that cannot be logically activated. This allows to strongly relax timing constraints while guaranteeing minimal an ...

2018

Combining Structural and Timing Errors in Overclocked Inexact Speculative Adders

Christian Enz, Vincent Frédéric Camus, Xun Jiao, Mattia Cacciotti, Yu Jiang

Worst-case design is used in IoT devices and high performance data centers to ensure reliability, leading to a power efficiency loss. Recently, approximate computing has been proposed to trade off accuracy for efficiency. In this paper, we use Inexact Spec ...

Ieee2017

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