Publications by Thomas Christoph Müller

A GRANDAB Decoder with 8.48 Gbps Worst-Case Throughput in 65nm CMOS

Andreas Peter Burg, Thomas Christoph Müller, Alexandre Sébastien Julien Levisse, Andreas Toftegaard Kristensen, Yifei Shen, Yuqing Ren

We present an error correction code (ECC) decoder based on the Guessing Random Additive Noise Decoding (GRAND) with ABandonment (GRANDAB) algorithm for applications that require constant throughput and fixed decoding latency in the Gbps range. This high co ...

IEEE Computer Society2024

X-HEEP: An Open-Source, Configurable and Extendible RISC-V Microcontroller

Ruben Rodriguez, David Atienza Alonso, Benoît Walter Denkinger, Thomas Christoph Müller, Miguel Peon Quiros, Saverio Nasturzio, Simone Machetti, Pasquale Davide Schiavone, José Angel Miranda Calero, Rubén Rodríguez Álvarez

In this work, we present eXtendible Heterogeneous Energy-Efficient Platform (X-HEEP), a configurable and extendible single-core RISC-V-based ultra-low-power microcontroller. X-HEEP can be used standalone as a low-cost microcontroller, or it can be integrat ...

New York2023

Adaptive Body Biasing in Strong Body Factor Technologies

Thomas Christoph Müller

With the advent of intelligent sensor nodes in everyday life, low power aspects of system design become more and more important. Adaptive body biasing is a promising methodology to achieve dynamic adaptation of the tradeoff between performance and energy b ...

EPFL2021

A 0.5 V 2.5 mu W/MHz Microcontroller with Analog-Assisted Adaptive Body Bias PVT Compensation with 3.13 nW/kB SRAM Retention in 55 nm Deeply-Depleted Channel CMOS

David Ruffieux, Andreas Peter Burg, Thomas Christoph Müller

Microcontroller systems operating at low supply voltage in near- or sub-threshold regime suffer both from increased effects of PVT (Process, Voltage, Temperature) variation and from a larger share of leakage on overall power due to the reduced frequency. W ...

IEEE2019

A 588-Gb/s LDPC Decoder Based on Finite-Alphabet Message Passing

Andreas Peter Burg, Alexios Konstantinos Balatsoukas Stimming, Adam Shmuel Teman, Reza Ghanaatian Jahromi, Thomas Christoph Müller

2018

PolarBear: A 28-nm FD-SOI ASIC for Decoding of Polar Codes

Andreas Peter Burg, Alexios Konstantinos Balatsoukas Stimming, Andrea Bonetti, Thomas Christoph Müller, Pascal Giard

Polar codes are a recently proposed class of block codes that provably achieve the capacity of various communication channels. They received a lot of attention as they can do so with low-complexity encoding and decoding algorithms, and they have an explici ...

2017

A Multi-Gbps Unrolled Hardware List Decoder Systematic Polar Code

Andreas Peter Burg, Alexios Konstantinos Balatsoukas Stimming, Thomas Christoph Müller, Pascal Giard

Polar codes are a new class of block codes with an explicit construction that provably achieve the capacity of various communications channels, even with the low-complexity successive-cancellation (SC) decoding algorithm. Yet, the more complex successive-c ...

2016

DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment

Andreas Peter Burg, Lorenz Flavio Schmid, Jeremy Hugues-Felix Constantin, Andrea Bonetti, Adam Shmuel Teman, Thomas Christoph Müller

This paper presents DynOR, a 32-bit 6-stage OpenRISC microprocessor with dynamic clock adjustment. To alleviate the issue of unused dynamic timing margins, the clock period of the processor is adjusted on a cycle-by-cycle level, based on the instruction ty ...

Ieee2016