Publications by Rishabh Ramesh Iyer

Automatically Reasoning About How Systems Code Uses the CPU Cache

George Candea, Aikaterini Argyraki, Rishabh Ramesh Iyer

We present a technique, called CFAR, that developers can use to reason precisely about how their code, as well as third-party code, uses the CPU cache. Given a piece of systems code P, CFAR employs program analysis and binary instrumentation to automatical ...

2024

The Case for Performance Interfaces for Hardware Accelerators

George Candea, Aikaterini Argyraki, Rishabh Ramesh Iyer, Jiacheng Ma

While systems designers are increasingly turning to hardware accelerators for performance gains, realizing these gains is painstaking and error-prone. It can take several person-months to determine if a given accelerator is a good fit for a given piece of ...

2023

Latency Interfaces for Systems Code

Rishabh Ramesh Iyer

This thesis demonstrates that it is feasible for systems code to expose a latency interface that describes its latency and related side effects for all inputs, just like the code's semantic interface describes its functionality and related side effects. S ...

EPFL2023

Achieving Microsecond-Scale Tail Latency Efficiently with Approximate Optimal Scheduling

George Candea, Rishabh Ramesh Iyer

Datacenter applications expect microsecond-scale service times and tightly bound tail latency, with future workloads expected to be even more demanding. To address this challenge, state-of-the-art runtimes employ theoretically optimal scheduling policies, ...

Assoc Computing Machinery2023

Performance Interfaces for Network Functions

George Candea, Aikaterini Argyraki, Rishabh Ramesh Iyer

Modern programmers routinely use third-party code, and infrastructure operators deploy software they did not write. This would not be possible without semantic interfaces---documentation, header files, specifications---that succinctly describe what that th ...

USENIX Association2022

Verifying Software Network Functions with No Verification Expertise

George Candea, Aikaterini Argyraki, Solal Vincenzo Pirelli, Rishabh Ramesh Iyer, Luis David Figueiredo Mascarenhas Moreira Pedrosa, Matteo Rizzo

We present the design and implementation of Vigor, a software stack and toolchain for building and running software network middleboxes that are guaranteed to be correct, while preserving competitive performance and developer productivity. Developers write ...

ACM2019

Performance Contracts for Software Network Functions

George Candea, Aikaterini Argyraki, Solal Vincenzo Pirelli, Arseniy Zaostrovnykh, Rishabh Ramesh Iyer, Luis David Figueiredo Mascarenhas Moreira Pedrosa

Software network functions (NFs), or middleboxes, promise flexibility and easy deployment of network services but face the serious challenge of unexpected performance behaviour. We propose the notion of a performance contract, a construct formulated in ter ...

USENIX ASSOC2019

Automated Synthesis of Adversarial Workloads for Network Functions

Aikaterini Argyraki, Jonas Fietz, Arseniy Zaostrovnykh, Rishabh Ramesh Iyer, Luis David Figueiredo Mascarenhas Moreira Pedrosa

Software network functions promise to simplify the deployment of network services and reduce network operation cost. However, they face the challenge of unpredictable performance. Given this performance variability, it is imperative that during deployment, ...

ACM2018