Publications by Dewmini Sudara Marakkalage

Logic Synthesis and Optimization for CMOS and Post-CMOS Technologies

Logic synthesis is a cornerstone of electronic design automation (EDA), facilitating the optimization of power, performance, and area (PPA) in integrated circuits. As complementary metal-oxide-semiconductor (CMOS) technology approaches its physical limitat ...

EPFL2025

Scalable Sequential Logic Synthesis Using Observability Don’t Care Conditions

Giovanni De Micheli, Dewmini Sudara Marakkalage

Sequential logic synthesis expands the solution space compared to combinational logic synthesis by reasoning about the reachable states of memory elements, leading to better Power-Performance-Area (PPA) outcomes. As gate costs continue to rise in advanced ...

2025

Technology-Aware Logic Synthesis for Superconducting Electronics

Giovanni De Micheli, Dewmini Sudara Marakkalage, Siang-Yun Lee, Alessandro Tempia Calvino, Mingfei Yu, Rassul Bairamkulov

Superconducting electronics provide us with cryogenic digital circuits that can rival established technologies in performance and energy consumption. Today, the lack of tools for the design of large-scale integrated superconducting circuits is a major obst ...

2024

Fanout-Bounded Logic Synthesis for Emerging Technologies - A Top-Down Approach

Giovanni De Micheli, Dewmini Sudara Marakkalage

In logic circuits, the number of fanouts a gate can drive is limited, and such limits are tighter in emerging technologies such as superconducting electronic circuits. In this work, we study the problem of resynthesizing a logic network with bounded-fanout ...

IEEE2023

Technology Mapping for Beyond-CMOS Circuitry with Unconventional Cost Functions

Giovanni De Micheli, Dewmini Sudara Marakkalage, Siang-Yun Lee

2023

Garbled Circuits Reimagined: Logic Synthesis Unleashes Efficient Secure Computation

Giovanni De Micheli, Dewmini Sudara Marakkalage, Mingfei Yu

Garbled circuit (GC) is one of the few promising protocols to realize general-purpose secure computation. The target computation is represented by a Boolean circuit that is subsequently transformed into a network of encrypted tables for execution. The need ...

MDPI2023

Fanout-Bounded Logic Synthesis for Emerging Technologies - A Top- Down Approach

Giovanni De Micheli, Dewmini Sudara Marakkalage

2022

Majority-based Design Flow for AQFP Superconducting Family

Giovanni De Micheli, Dewmini Sudara Marakkalage, Siang-Yun Lee, Alessandro Tempia Calvino

Adiabatic superconducting devices are promising candidates to develop high-speed/low-power electronics. Advances in physical technology must be matched with a systematic development of comprehensive design and simulation tools to bring superconducting elec ...

IEEE2022

Three-Input Gates for Logic Synthesis

Giovanni De Micheli, Eleonora Testa, Mathias Soeken, Dewmini Sudara Marakkalage, Heinz Riener

Most logic synthesis algorithms work on graph representations of logic functions with nodes associated with arbitrary logic expressions or simple logic functions and iteratively optimize such graphs. While recent multilevel logic synthesis efforts focused ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2021

Optimizing Adiabatic Quantum-Flux-Parametron (AQFP) Circuits using an Exact Database

Giovanni De Micheli, Dewmini Sudara Marakkalage

Adiabatic Quantum-Flux-Parametron (AQFP) is a family of superconducting electronic (SCE) circuits exhibiting high energy efficiency. In AQFP technology, logic gates require splitters to drive multiple fanouts and both the logic gates and the splitters are ...

IEEE2021

Three-Input Gates for Logic Synthesis

Giovanni De Micheli, Eleonora Testa, Mathias Soeken, Dewmini Sudara Marakkalage, Heinz Riener

2020