Publications related to NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic Element

Contemporary Logic Synthesis: with an Application to AQFP Circuit Optimization

Electronic devices play an irreplaceable role in our lives. With the tightening time to market, exploding demand for computing power, and continuous desire for smaller, faster, less energy-consuming, and lower-cost chips, computer-aided design for electron ...

EPFL2024

Snap buckling of bistable beams under combined mechanical and magnetic loading

Pedro Miguel Nunes Pereira de Almeida Reis, Dong Yan, Tomohiko Sano, Arefeh Abbasi

We investigate the mechanics of bistable, hard-magnetic, elastic beams, combining experiments, finite-element modelling (FEM) and a reduced-order theory. The beam is made of a hard magneto-rheological elastomer, comprising two segments with antiparallel ma ...

ROYAL SOC2023

Improving Standard-Cell Design Flow using Factored Form Optimization

Giovanni De Micheli, Alessandro Tempia Calvino

Factored form is a powerful multi-level representation of a Boolean function that readily translates into an implementation of the function in CMOS technology. In particular, the number of literals in a factored form correlates strongly with the number of ...

IEEE2023

Automating the Design of Programmable Interconnect for Reconfigurable Architectures

Stefan Nikolic

With Moore's law coming to an end, increasingly more hope is being put in specialized hardware implemented on reconfigurable architectures such as Field-Programmable Gate Arrays (FPGAs). Yet, it is often neglected that these architectures themselves experi ...

EPFL2023

High-order geometric integrators for nonadiabatic molecular quantum dynamics and their applications to explore conical intersections

Seonghoon Choi

Accurate simulations of molecular quantum dynamics are crucial for understanding numerous natural processes and experimental results. Yet, such high-accuracy simulations are challenging even for relatively simple systems where the Born-Oppenheimer approxim ...

EPFL2022

Three-Input Gates for Logic Synthesis

Giovanni De Micheli, Eleonora Testa, Mathias Soeken, Dewmini Sudara Marakkalage, Heinz Riener

Most logic synthesis algorithms work on graph representations of logic functions with nodes associated with arbitrary logic expressions or simple logic functions and iteratively optimize such graphs. While recent multilevel logic synthesis efforts focused ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2021

Random flip-flop: adding quantum randomness to digital circuits for improved cyber security, artificial intelligence and more

Claudio Bruschini, Edoardo Charbon, Ivan Michel Antolovic, Mario Stipcevic

Harnessing quantum randomness for the generation of random numbers is an important concept crucial for information security and many other computer-related applications. Quantum random number generators (QRNGs) are evolving from bulky, slow, and expensive ...

SPIE2021

Miss-Optimized Memory Systems: Turning Thousands of Outstanding Misses into Reuse Opportunities

Mikhail Asiatici

Even if Dennard scaling came to an end fifteen years ago, Moore' s law kept fueling an exponential growth in compute performance through increased parallelization. However, the performance of memory and, in particular, Dynamic Random Access Memory (DRAM), ...

EPFL2021

Programmable Logic Gates Based On Tunable Multistable Mechanisms

Simon Nessim Henein, Ilan Vardi, Mohamed Gamal Abdelrahman Ahmed Zanaty, Hubert Pierre-Marie Benoît Schneegans

Binary logic operations are the building blocks of computing machines. In this paper, we present a new programmable binary logic gate based on programmable multistable mechanisms (PMM), which are multistable structures whose stability behavior depends on m ...

AMER SOC MECHANICAL ENGINEERS2020

Reconfigurable Logic Gates Based on Programable Multistable Mechanisms

Simon Nessim Henein, Ilan Vardi, Mohamed Gamal Abdelrahman Ahmed Zanaty, Hubert Pierre-Marie Benoît Schneegans

Binary logic gates are building blocks of computing machines, in particular, electronic computers. One variant is the programable logic gate, also known as the reconfigurable logic gate, in which the logical function implemented can be modified. In this pa ...

2020

Data Structures and Algorithms for Logic Synthesis in Advanced Technologies

Eleonora Testa

Logic synthesis is a key component of digital design and modern EDA tools; it is thus an essential instrument for the design of leading-edge chips and to push the limits of their performance. In the last decades, the electronic circuits community has evolv ...

EPFL2020

Extending Boolean Methods for Scalable Logic Synthesis

Giovanni De Micheli, Luca Gaetano Amarù, Pierre-Emmanuel Julien Marc Gaillardon, Eleonora Testa, Mathias Soeken

In recent years, Boolean methods in logic synthesis have been drawing the attention of EDA researchers due to the continuous push to advance quality of results. Boolean methods require high computational cost, as they rely on complete functional properties ...

2020

Enabling Accuracy-Aware Quantum Compilers using Symbolic Resource Estimation

Giulia Meuli, Mathias Soeken

Approximation errors must be taken into account when compiling quantum programs into a low-level gate set. We present a methodology that tracks such errors automatically and then optimizes accuracy parameters to guarantee a specified overall accuracy while ...

ASSOC COMPUTING MACHINERY2020

Computational characteristics and hardware implications of brain tissue simulations

Francesco Cremonesi

Understanding the link between the brain's anatomy and its function through computer simulations of neural tissue models is a widely used approach in computational neuroscience. This technique enables rapid prototyping and testing of hypotheses, allowing r ...

EPFL2019

A new analysis approach for T-2 relaxometry myelin water quantification: Orthogonal Matching Pursuit

Guillaume Jean Op 't Veld

Purpose: In vivo myelin quantification can provide valuable noninvasive information on neuronal maturation and development, as well as insights into neurological disorders. Multiexponential analysis of multiecho T-2 relaxation is a powerful and widely appl ...

Wiley2019

Improvements to Boolean resynthesis

Giovanni De Micheli, Luca Gaetano Amarù, Mathias Soeken

In electronic design automation Boolean resynthesis techniques are increasingly used to improve the quality of results where algebraic methods hit local minima Boolean methods rely on complete functional properties of a logic circuit, preferably including ...

IEEE2018

Functional Decomposition Using Majority

Giovanni De Micheli, Mathias Soeken, Zhufei Chu

Typical operators for the decomposition of Boolean functions in state-of-the-art algorithms are AND, exclusive-OR (XOR), and a 2-to-1 multiplexer (MUX). We propose a logic decomposition algorithm that uses the majority-of-three (MAJ) operation. Such decomp ...

IEEE2018

Post-P&R Performance and Power Analysis for RRAM-based FPGAs

Giovanni De Micheli, Xifan Tang, Pierre-Emmanuel Julien Marc Gaillardon, Edouard Giacomin

Resistive Random Access Memory (RRAM)-based FPGAs are predicted to outperform conventional FPGAs architectures in area, delay and power over a wide range of voltage operations, allowing novel energy-quality trade-offs for reconfigurable computing. The oppo ...

2018

Resistive random access memory based multiplexers and field programmable gate arrays

Giovanni De Micheli, Gain Kim, Xifan Tang, Pierre-Emmanuel Julien Marc Gaillardon, Edouard Giacomin

Resistive random access memory (RRAM) based multiplexers and field programmable gate arrays (FPGAs) are provided. The RRAM-based multiplexers and FPGAs include a 4T1R programming structure to program the RRAMs. The programming structure includes two progra ...

2018

FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs

Giovanni De Micheli, Xifan Tang, Pierre-Emmanuel Julien Marc Gaillardon, Edouard Giacomin

In this paper, we developed a simulation-based architecture evaluation framework for field-programmable gate arrays (FPGAs), called FPGA-SPICE, which enables automatic layout-level estimation and electrical simulations of FPGA architectures. FPGA-SPICE can ...

2018