Design of Low-power Analog Circuits in Advanced Technology Nodes using the Gm/ID Approach

The Gm/ID approach has proven to be an efficient technique for the design of low-power analog circuits. Until now it was mostly demonstrated on older CMOS technology nodes. In this paper we will show that the Gm/ID methodology still holds for advanced technologies using the simplified EKV model which only requires 4 parameters for bulk and 5 for FDSOI. We will start with a brief presentation of the simplified EKV model highlighting how the normalization process can strip- off most of the technology dependence. Then we will introduce the concept of inversion coefficient IC and show that the normalized Gm/ID only depends on IC and a parameter λc accounting for velocity saturation. Then we will show how to extract the few parameters needed from data either generated from the PDK or from measurements. We then will illustrate the methodology by a design example of an OTA in a 22nm FDSOI technology. The design is then validated by simulations using the founder PDK using the full BSIM-IMG compact model demonstrating an excellent agreement between the simulation results and the specifications despite the simplicity of the model and the methodology.