Publications related to Asymmetrically strained all-silicon multi-gate n-Tunnel FETs

Enhancement-mode Multi-channel AlGaN/GaN Transistors with LiNiO Junction Tri-Gate

Elison de Nazareth Matioli, Taifang Wang, Luca Nela

Multi-channel GaN power device, consisting of stacking multiple two-dimensional-electron-gas (2DEG) channels, has been demonstrated to achieve unprecedented on-state performance while maintaining high breakdown voltage (VBR). However, the large carrier den ...

Institute of Electrical and Electronics Engineers2022

High-Temperature HEMT Mode

Farzan Jazaeri, Nika Sahebghalam

Taking into account the impact of self-heating and temperature rise effects, this work presents a physics-based analytical model for HEMTs, operating continuously from room temperature to high temperatures in linear and saturation regimes. Relying on the c ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Exploring negative capacitance and neuromorphic devices based on CMOS-compatible ferroelectric HfO2

Carlotta Gastaldi

Ferroelectric materials are explored for numerous applications thanks to their properties associated with electrically switchable spontaneous polarization. Perovskites are an established class of ferroelectrics used for sensors and actuators. However, they ...

EPFL2022

LiNiO Junction Gate for High-performance Enhancement-mode GaN Power Transistor

Taifang Wang

GaN metal-oxide-semiconductor high electron mobility transistors (MOS)HEMTs) offer outstanding properties for next-generation power electronics devices. The high conductivity, high voltage blocking capability, high operation frequency, and device-level int ...

EPFL2022

P-GaN Tri-Gate MOS Structure for Normally-Off GaN Power Transistors

Elison de Nazareth Matioli, Jun Ma, Minghua Zhu, Pirouz Sohi, Catherine Erine, Mohammad Samizadeh Nikooytabalvandani, Luca Nela

In this letter, we present a new concept for normally-off AlGaN/GaN-on-Si MOS-HEMTs based on the combination of p-GaN, tri-gate and MOS structures to achieve high threshold voltage (V-TH) and low on-resistance (R-ON). The p-GaN is used to engineer the band ...

Institute of Electrical and Electronics Engineers2021

Enhancement Mode Tri-gate GaN Power Devices and Logic Circuits

Minghua Zhu

Gallium Nitride (GaN) is one of the most promising materials for high frequency power switching due to its exceptional properties such as large saturation velocity, high carrier mobility, and high breakdown field strength. The high switching frequency of G ...

EPFL2021

Characterization and Modeling of Total Ionizing Dose Effects on Nanoscale MOSFETs for Particle Physics Experiments

Chunmin Zhang

Total ionizing radiation compromises electrical characteristics of microelectronic devices and even causes functional failures of integrated circuits. It has been identified as a potential threat to electronic components, especially those in high-energy ph ...

EPFL2021

In-depth Cryogenic Characterization of 22 nm FDSOI Technology for Quantum Computation

Christian Enz, Edoardo Charbon, Farzan Jazaeri, Hung-Chi Han, Antonio D'Amico

In this paper, the influence of temperature and back-gate bias is experimentally investigated on 22 nm FDSOI CMOS process. Cryogenic DC characterization was carried out under various back-gate voltages, V back , from 2.95 K back to 300 K. An abrupt drop-of ...

IEEE2021

Multi-channel nanowire devices for efficient power conversion

Elison de Nazareth Matioli, Jun Ma, Vasiliki Tileli, Taifang Wang, Tzu-Hsien Shen, Catherine Erine, Luca Nela

Nanowire-based devices can potentially be of use in a variety of electronic applications, from ultrascaled digital circuits to 5G communication networks. However, the devices are typically restricted to low-power applications due to the relatively low elec ...

2021

WSe2/SnSe2 vdW heterojunction Tunnel FET with subthermionic characteristic and MOSFET co-integrated on same WSe2 flake

Mihai Adrian Ionescu, Nicolò Oliva, Matteo Cavalieri, Luca Capua

Two-dimensional/two-dimensional (2D/2D) heterojunctions form one of the most versatile technological solutions for building tunneling field effect transistors because of the sharp and potentially clean interfaces resulting from van der Waals assembly. Seve ...

NATURE PUBLISHING GROUP2020

Free Carrier Mobility, Series Resistance, and Threshold Voltage Extraction in Junction FETs

Matthias Bucher, Jean-Michel Sallese, Farzan Jazaeri

In this brief, extraction methods are proposed for determining the essential parameters of double gate junction field-effect transistors (FETs). First, a novel method for determining free carrier effective mobility, similar to a recently proposed method fo ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

Investigation of p-GaN tri-Gate normally-Off GaN Power MOSHEMTs

Elison de Nazareth Matioli, Jun Ma, Minghua Zhu

In this work, we present the investigation of the combination of p-GaN gate and tri-gate structures to achieve normally-off operation on GaN-on-Si MOSFETs. We have developed and optimized a selective and low-damage p-GaN etching recipe to stop at the AlGaN ...

IEEE2020

Nanowire Tunnel FET with Simultaneously Reduced Subthermionic Subthreshold Swing and Off-Current due to Negative Capacitance and Voltage Pinning Effects

Igor Stolichnov, Mihai Adrian Ionescu, Teodor Rosca, Ali Saeidi, Matteo Cavalieri

Nanowire tunnel field-effect transistors (TFETs) have been proposed as the most advanced one-dimensional (1D) devices that break the thermionic 60 mV/decade of the subthreshold swing (SS) of metal oxide semiconductor field-effect transistors (MOSFETs) by u ...

AMER CHEMICAL SOC2020

Physical Model of Low-Temperature to Cryogenic Threshold Voltage in MOSFETs

Christian Enz, Farzan Jazaeri, Arnout Lodewijk M Beckers

This article presents a physical model of the threshold voltage in MOSFETs valid down to 4.2 K. Interface traps close to the band edge modify the saturating temperature behavior of the threshold voltage observed in cryogenic measurements. Dopant freezeout, ...

2020

Subthermionic negative capacitance ion sensitive field-effect transistor

Mihai Adrian Ionescu, Ali Saeidi, Francesco Bellando, Carlotta Gastaldi

One of the main advantages of Ion-Sensitive Field-Effect Transistor (ISFET) technology is the capability to exploit technological advancements initially developed for conventional FETs for logic applications, such as the employ of high-k dielectrics for th ...

2020

Sweat monitoring with CMOS compatible technology: ISFETS and beyond

Francesco Bellando

In recent years, sweat has gained increasing attention from the scientific community as a new analyte for health monitoring. The main advantage with respect to the "Gold Standard" for laboratory analysis, i.e. blood, is of course the possibility of perform ...

EPFL2020

Quantum Transport in 40-nm MOSFETs a Deep-Cryogenic Temperatures

Edoardo Charbon, Andrea Ruffino, Yatao Peng

In this letter, we characterize the electrical properties of commercial bulk 40-nm MOSFETs at room and deep cryogenic temperatures, with a focus on quantum information processing (QIP) applications. At 50 mK, the devices operate as classical FETs or quantu ...

Institute of Electrical and Electronics Engineers2020

Deep-UV-Enhanced Approach for Low-Temperature Solution Processing of IZO Transistors with High-k AlOx/YAlOx Dielectric

Danick Briand, Alessio Mancinelli, Jaemin Kim

Solution processing is an attractive alternative to standard vacuum fabrication techniques for the large-area manufacturing of metal oxide (MOx)-based electron devices. Here, we report on thin-film transistors (TFTs) based on a solution-processed indium zi ...

AMER CHEMICAL SOC2020

Co-integrated Subthermionic 2D/2D WSe2/SnSe2 Vertical Tunnel FET and WSe2 MOSFET on same flake: towards a 2D/2D vdW Dual-Transport Steep Slope FET

Mihai Adrian Ionescu, Nicolò Oliva, Matteo Cavalieri, Luca Capua

In this work we report the fabrication, co-integration and resulting performance of 2D/2D van der Waals (vdW) Vertical p-type Tunnel FETs and p-MOSFETs in a WSe2/SnSe2 material system. We demonstrate the best ever reported combined performance in terms of ...

IEEE2019

Negative Capacitance as Universal Digital and Analog Performance Booster for Complementary MOS Transistors

Christian Enz, Igor Stolichnov, Mihai Adrian Ionescu, Farzan Jazaeri, Ali Saeidi

Boltzmann electron energy distribution poses a fundamental limit to lowering the energy dissipation of conventional MOS devices, a minimum increase of the gate voltage, i.e. 60 mV, is required for a 10-fold increase in drain-to-source current at 300 K. Neg ...

Nature Research2019