Publication

Sub-100 nm-scale Aluminum Nanowires by Stencil Lithography: Fabrication and Characterization

Jürgen Brugger, Luis Guillermo Villanueva Torrijo, Andreea Veronica Savu, Marc Antonius Friedrich van den Boogaart, Oscar Vazquez Mena, Katrin Sidler Arnet
2008
Conference Papers

Abstract

We present the fabrication process and electrical characterization of sub-100 nm scale Al nanowires (NWs) fabricated by stencil lithography (SL). We use a stencil with sub- 100 nm wide nanoslits patterned by focused ion beam (FIB) milling. The stencil is aligned and clamped onto a substrate containing predefined electrical contacts. Then a 60 nm-thick layer of Aluminum (Al) is deposited through the stencil producing NWs with lengths of ~1, 2 and 5 μm and widths down to 65 nm. The NWs show an ohmic behavior with values varying from 30 Ω up to 300 Ω, depending on the dimensions of the structures. We have extracted a resistivity for the Al NWs of ~10 x 10-8 Ωm. We also show that stencils can be cleaned and reused, proving that SL is a cost-efficient and scalable manufacturing method for the direct fabrication of metallic NWs on a full wafer scale.

Official source

https://infoscience.epfl.ch/entities/publication/882ff2d8-9dc8-4fe7-a62e-2221c05edaa9

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Jürgen Brugger, Luis Guillermo Villanueva Torrijo, Andreea Veronica Savu, Marc Antonius Friedrich van den Boogaart, Oscar Vazquez Mena, Katrin Sidler Arnet
2008
Conference Papers

Abstract

Official source

https://infoscience.epfl.ch/entities/publication/882ff2d8-9dc8-4fe7-a62e-2221c05edaa9

About this result

Related concepts (23)

Semiconductor device fabrication

Semiconductor device fabrication is the process used to manufacture semiconductor devices, typically integrated circuits (ICs) such as computer processors, microcontrollers, and memory chips (such as NAND flash and DRAM) that are present in everyday electrical and electronic devices. It is a multiple-step photolithographic and physio-chemical process (with steps such as thermal oxidation, thin-film deposition, ion-implantation, etching) during which electronic circuits are gradually created on a wafer, typically made of pure single-crystal semiconducting material.

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Fused filament fabrication (FFF), also known as fused deposition modeling (with the trademarked acronym FDM), or filament freeform fabrication, is a 3D printing process that uses a continuous filament of a thermoplastic material. Filament is fed from a large spool through a moving, heated printer extruder head, and is deposited on the growing work. The print head is moved under computer control to define the printed shape.

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The 65 nm process is an advanced lithographic node used in volume CMOS (MOSFET) semiconductor fabrication. Printed linewidths (i.e. transistor gate lengths) can reach as low as 25 nm on a nominally 65 nm process, while the pitch between two lines may be greater than 130 nm. For comparison, cellular ribosomes are about 20 nm end-to-end. A crystal of bulk silicon has a lattice constant of 0.543 nm, so such transistors are on the order of 100 atoms across. By September 2007, Intel, AMD, IBM, UMC and Chartered were also producing 65 nm chips.

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