Publications related to Swap and Rotate: Lightweight Linear Layers for SPN-based Blockciphers

BBB security for 5-round even-Mansour-based key-alternating Feistel ciphers

In this paper, we study the security of the Key-Alternating Feistel (KAF) ciphers, a class of key alternating ciphers with the Feistel structure, where each round of the cipher is instantiated with n-bit public round permutation Pi\documentclass[12pt]{mini ...

SPRINGER2023

Green Cryptography and Other Optimisations

Andrea Felice Caforio

The spectral decomposition of cryptography into its life-giving components yields an interlaced network of tangential and orthogonal disciplines that are nonetheless invariably grounded by the same denominator: their implementation on commodity computing p ...

EPFL2023

PAE: Towards More Efficient and BBB-Secure AE from a Single Public Permutation

Ritam Bhaumik

Four recent trends have emerged in the evolution of authenticated encryption schemes: (1) Regarding simplicity, the adoption of public permutations as primitives allows for sparing a key schedule and the need for storing round keys; (2) using the sums of p ...

Springer2023

Revisiting the Indifferentiability of the Sum of Permutations

Ritam Bhaumik

The sum of two n-bit pseudorandom permutations is known to behave like a pseudorandom function with n bits of security. A recent line of research has investigated the security of two public n-bit permutations and its degree of indifferentiability. Mandal e ...

Springer2023

DASS: Combining Dynamic & Static Scheduling in High-Level Synthesis

Paolo Ienne, Lana Josipovic

A central task in high-level synthesis is scheduling: the allocation of operations to clock cycles. The classic approach to scheduling is static, in which each operation is mapped to a clock cycle at compile-time, but recent years have seen the emergence o ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

An All-Digital 1 Mbps, 57 pJ/bit Bluetooth Low Energy (BLE) Backscatter ASIC in 65 nm CMOS

James Daniel Rosenthal

We present an all-digital application specific integrated circuit (ASIC) that implements Bluetooth Low Energy (BLE)-compatible backscatter communication. The ASIC was fabricated in a 65 nm CMOS process and occupies an active area of 0.12 mm(2) while consum ...

IEEE2022

From Trees to Barcodes and Back Again: A Combinatorial, Probabilistic and Geometric Study of a Topological Inverse Problem

Adélie Eliane Garin

In this thesis, we investigate the inverse problem of trees and barcodes from a combinatorial, geometric, probabilistic and statistical point of view. Computing the persistent homology of a merge tree yields a barcode B. Reconstructing a tree from B invol ...

EPFL2022

Serial Lightweight Implementation Techniques for Block Ciphers

Muhammed Fatih Balli

Most of the cryptographic protocols that we use frequently on the internet are designed in a fashion that they are not necessarily suitable to run in constrained environments. Applications that run on limited-battery, with low computational power, or area ...

EPFL2021

Random flip-flop: adding quantum randomness to digital circuits for improved cyber security, artificial intelligence and more

Claudio Bruschini, Edoardo Charbon, Ivan Michel Antolovic, Mario Stipcevic

Harnessing quantum randomness for the generation of random numbers is an important concept crucial for information security and many other computer-related applications. Quantum random number generators (QRNGs) are evolving from bulky, slow, and expensive ...

SPIE2021

Efficient Bootstrapping for Approximate Homomorphic Encryption with Non-sparse Keys

Jean-Pierre Hubaux, Jean-Philippe Léonard Bossuat, Christian Vincent Mouchet, Juan Ramón Troncoso-Pastoriza

We present a bootstrapping procedure for the full-RNS variant of the approximate homomorphic-encryption scheme of Cheon et al., CKKS (Asiacrypt 17, SAC 18). Compared to the previously proposed procedures (Eurocrypt 18 & 19, CT-RSA 20), our bootstrapping pr ...

SPRINGER INTERNATIONAL PUBLISHING AG2021

Low Noise Clock Generation: Modeling, Analysis and Implementation

Duygu Kostak

The aim of this thesis is to implement, analyze and improve the selected low noise clock generation and distribution techniques for ADC implementations. The thesis is divided into two parts. The first part focuses on the sampling phase generation and distr ...

EPFL2021

Further Results on Efficient Implementations of Block Cipher Linear Layers

Subhadeep Banik

At the FSE conference of ToSC 2018, Kranz et al. presented their results on shortest linear programs for the linear layers of several well known block ciphers in literature. Shortest linear programs are essentially the minimum number of 2-input xor gates r ...

2021

Improving First-Order Threshold Implementations of SKINNY

Andrea Felice Caforio, Ognjen Glamocanin, Subhadeep Banik, Daniel Patrick Collins

Threshold Implementations have become a popular generic technique to construct circuits resilient against power analysis attacks.In this paper, we look to devise efficient threshold circuits for the lightweight block cipher family SKINNY. The only threshol ...

Springer2021

A Deeper Look at the Energy Consumption of Lightweight Block Ciphers

Francesco Regazzoni, Andrea Felice Caforio, Muhammed Fatih Balli, Subhadeep Banik

In the last few years, the field of lightweight cryptography has seen an influx in the number of block ciphers and hash functions being proposed. In the past there have been numerous papers that have looked at circuit level implementation of block ciphers ...

IEEE2021

Combining Dynamic & Static Scheduling in High-level Synthesis

Paolo Ienne, Lana Josipovic

A central task in high-level synthesis is scheduling: the allocation of operations to clock cycles. The classic approach to scheduling is static, in which each operation is mapped to a clock cycle at compile-time, but recent years have seen the emergence o ...

ASSOC COMPUTING MACHINERY2020

The Area-Latency Symbiosis: Towards Improved Serial Encryption Circuits

Andrea Felice Caforio, Muhammed Fatih Balli, Subhadeep Banik

The bit-sliding paper of Jean et al. (CHES 2017) showed that the smallest-size circuit for SPN based block ciphers such as AES, SKINNY and PRESENT can be achieved via bit-serial implementations. Their technique decreases the bit size of the datapath and na ...

2020

Low-Power Design of Digital VLSI Circuits around the Point of First Failure

Andrea Bonetti

As an increase of intelligent and self-powered devices is forecasted for our future everyday life, the implementation of energy-autonomous devices that can wirelessly communicate data from sensors is crucial. Even though techniques such as voltage scaling ...

EPFL2019

Exploring Lightweight Efficiency of Forkaes

Muhammed Fatih Balli, Subhadeep Banik

Recently the ForkAES construction was proposed by Andreeva et al. for efficiently performing authenticated encryption of very short messages on next generation IoT devices. The ForkAES tweakable block cipher uses around one and a half AES encryption calls ...

Springer2019

Compact Circuits for Combined AES Encryption/Decryption

Subhadeep Banik

The implementation of the AES encryption core by Moradi et al. at Eurocrypt 2011 is one of the smallest in terms of gate area. The circuit takes around 2400 gates and operates on an 8 bit datapath. However this is an encryption only core and unable to cate ...

2019

Triboelectric‐TFT Flip‐Flop for Bistable Latching of Dielectric Elastomer Actuators

Herbert Shea, Danick Briand, Rubaiyet Iftekharul Haque, Alexis Pierre Henri Marette, Xiaobin Ji, Ronan Julien Hinchet

A high‐voltage flip‐flop combining two self‐powered soft sensors with a flexible high‐voltage thin film transistor (HVTFT) is reported, and is used to electrically latch dielectric elastomer actuators (DEAs) in zero and high‐strain states. Two touch‐actuat ...

2019