Highly sensitive vertical hall sensors in CMOS technology

Vertical Hall sensors are capable of measuring surface-parallel components of the magnetic field. They allow therefore relatively easy conception of single-chip multi-axial magnetic sensors compared to solutions using horizontal Hall plates. The modern trend in the field of Hall sensors is to integrate them into electronic circuitry for signal processing. Before this thesis, highly sensitive vertical Hall sensors completely compatible to a technology adequate for co-integration of electronic circuitry were not available. This is the reason why we present in this thesis the developed knowledge that is necessary for the design and manufacture of highly sensitive vertical Hall sensors in CMOS technology. We first present the principles of the technology choice. A wide selection of CMOS processes is presently available, but in order to obtain optimal sensitivity we have to choose "the right" one. The performances can vary easily by 50% from one technology to another. The best choice are CMOS high-voltage technologies since they deliver n-diffusion layers with relatively low doping level and deep junction depth. We present a novel layout of vertical Hall sensors that has six contacts in the active sensor zone and is a development of the known layout that uses only four contacts. The additional contacts improve the sensitivity and reduce the systematic offset considerably. If we re-use layouts that were optimal for not-CMOS compatible technologies, we will see that the results are not satisfying. We have to develop our specific design parameters that are optimal for the chosen technology. The key for high sensitivities is the strong miniaturization of the devices down to technological limits given by the design rules, but sometimes even beyond that. Some of the design rules can be broken with benefit for the obtained sensor devices. In general, minimum contact sizes and contact distances are preferable as well as a minimum sensor thickness. The difficulty is however to find the absolute minimum before device degradation or even failure will occur. Our optimized sensors achieved voltage related sensitivities of about 0.04 V/(VT) and current related-sensitivities up to 400 V/(AT) that are comparable to existing CMOS compatible horizontal Hall plates. Such sensitivities were never reported for a standard CMOS process, without any additional pre- or post-processing steps. The miniaturization of the Hall devices has however also negative aspects e.g. an increase in sensor offset, noise and output non-linearity. Although Hall sensors have many advantages in comparison to other magnetic sensors (simple structure, low fabrication costs, very good linearity, robustness) they have the drawback of a big Abstract offset voltage that is often too big for many applications. This is why an enormous effort was made by researchers in the past to develop offset reduction methods for horizontal Hall plates. We state in this thesis that, in principle, the same techniques