Publication

Modeling and Simulation of Multi-Discipline Systems using Bond Graphs and VHDL-AMS

Alain Vachoux, Christophe Lallement
2005
Conference Papers

Abstract

Bond graphs represent a convenient tool for physical system analysis. While it is one part of the job to establish a pertinent bond graph model, it is another important part of the job to take advantage of this bond graph. A simulation tool is involved and the engineer effort varies depending on the sofware entry and computer issues. The paper focuses on the coherence of VHDL-AMS with regards to bond graphs. The objective is twofold. First the authors detail an experience on how to shift from a bond graph representation to a efficient VHDL-AMS code. Two practical examples are presented: a simple Pb-Fe battery and an air-bag application. The essential of the language with respect to bond graphs is recalled. Second the authors discuss several advantages and limitations of the language with respect to other available languages and tools when it comes to modeling bond graphs. Then some possible evolutions for the next IEEE 1076.1 VHDL-AMS standard are outlined.

Official source

https://infoscience.epfl.ch/entities/publication/da3c3bf6-3956-4f6e-936d-c896d54fbd89

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Alain Vachoux, Christophe Lallement
2005
Conference Papers

Abstract

Official source

https://infoscience.epfl.ch/entities/publication/da3c3bf6-3956-4f6e-936d-c896d54fbd89

About this result

Related concepts (12)

VHDL

The VHSIC Hardware Description Language (VHDL) is a hardware description language (HDL) that can model the behavior and structure of digital systems at multiple levels of abstraction, ranging from the system level down to that of logic gates, for design entry, documentation, and verification purposes. Since 1987, VHDL has been standardized by the Institute of Electrical and Electronics Engineers (IEEE) as IEEE Std 1076; the latest version of which is IEEE Std 1076-2019.

Accellera

Accellera Systems Initiative (Accellera) is a standards organization that supports a mix of user and vendor standards and open interfaces development in the area of electronic design automation (EDA) and integrated circuit (IC) design and manufacturing. It is less constrained than the Institute of Electrical and Electronics Engineers (IEEE) and is therefore the starting place for many standards. Once mature and adopted by the broader community, the standards are usually transferred to the IEEE.

Dual graph

In the mathematical discipline of graph theory, the dual graph of a planar graph G is a graph that has a vertex for each face of G. The dual graph has an edge for each pair of faces in G that are separated from each other by an edge, and a self-loop when the same face appears on both sides of an edge. Thus, each edge e of G has a corresponding dual edge, whose endpoints are the dual vertices corresponding to the faces on either side of e.

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