Publication

Delay Optimum And Area Optimal Mapping Of k-LUT Based FPGA Circuits

2009
Journal Articles

Abstract

The paper presents several improvements to our synthesis platform Xsynth that was developed targeting advanced logic synthesis and technological mapping for k-LUT based FPGAs. Having implemented an efficient exhaustive k-feasible cone generator it was targeted delay optimum mapping and optimal area. Implemented algorithm can use common unit-delay model and, the more general, the edge-delay model. The last model allows arbitrary delay values assignments to each branch of a circuit net. Such arbitrary delay values my reflect estimates of placement and routing delays. Powerful heuristics targeting minimal area (number of used LUTs in the mapped network) allow determinations of delay minimum solutions but having low used area.

Official source

https://infoscience.epfl.ch/entities/publication/ecd6fdad-1adf-467b-9510-a47a084d169c

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2009
Journal Articles

Abstract

Official source

https://infoscience.epfl.ch/entities/publication/ecd6fdad-1adf-467b-9510-a47a084d169c

About this result

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A field-programmable gate array (FPGA) is an integrated circuit designed to be configured after manufacturing. The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC). Circuit diagrams were previously used to specify the configuration, but this is increasingly rare due to the advent of electronic design automation tools. FPGAs contain an array of programmable logic blocks, and a hierarchy of reconfigurable interconnects allowing blocks to be wired together.

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