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Publications associées (29)

Physical Design Considerations of One-level RRAM-based Routing Multiplexers

Giovanni De Micheli, Xifan Tang, Pierre-Emmanuel Julien Marc Gaillardon, Edouard Giacomin

Resistive Random Access Memory (RRAM) technology opens the opportunity for granting both high-performance and low- power features to routing multiplexers. In this paper, we study the physical design considerations related to RRAM- based routing mult ...

ACM2017

Circuit Designs of High-Performance and Low-Power RRAM-Based Multiplexers Based on 4T(ransistor)1R(RAM) Programming Structure

Giovanni De Micheli, Xifan Tang, Pierre-Emmanuel Julien Marc Gaillardon, Edouard Giacomin

Routing multiplexers based on pass-transistors or transmission gates are an essential components in many digital integrated circuits. However, whatever structure is employed, CMOS multiplexers have two major limitations: 1) their delay is linearly related ...

Ieee-Inst Electrical Electronics Engineers Inc2017

Fast Hierarchical NPN Classification

Giovanni De Micheli, Paolo Ienne, Mathias Soeken, Ana Petkovska

Classifying functions according to some common properties into libraries of functions is an important step in many logic synthesis and technology mapping algorithms used in FPGA design flows. NPN classification is one of the frequently used classifications ...

IEEE2016

Boolean logic optimization in majority-inverter graphs

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù

We present a Boolean logic optimization framework based on Majority-Inverter Graph (MIG). An MIG is a directed acyclic graph consisting of three-input majority nodes and regular/complemented edges. Current MIG optimization is supported by a consistent alge ...

2016

Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance

Andreas Peter Burg, Georgios Karakonstantis, Jeremy Hugues-Felix Constantin, Anupam Chattopadhyay, Zheng Wang

This paper proposes a novel approach to modeling of gate level timing errors during high-level instruction set simulation. In contrast to conventional, purely random fault injection, our physically motivated approach directly relates to the underlying circ ...

ACM2016

Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance

Andreas Peter Burg, Georgios Karakonstantis, Jeremy Hugues-Felix Constantin, Anupam Chattopadhyay, Zheng Wang

This paper proposes a novel approach to modeling of gate level timing errors during high-level instruction set simulation. hi contrast to conventional, purely random fault injection, our physically motivated approach directly relates to the underlying circ ...

Ieee2016

Majority-Inverter Graph: A New Paradigm for Logic Optimization

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù

In this paper, we propose a paradigm shift in representing and optimizing logic by using only majority (MAJ) and inversion (INV) functions as basic operations. We represent logic functions by Majority-Inverter Graph (MIG): a directed acyclic graph c ...

Ieee-Inst Electrical Electronics Engineers Inc2016

Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement

Andreas Peter Burg, Adam Shmuel Teman, Luca Benini, Pascal Andreas Meinerzhagen

Embedded memory remains a major bottleneck in current integrated circuit design in terms of silicon area, power dissipation, and performance; however, static random access memories (SRAMs) are almost exclusively supplied by a small number of vendors throug ...

Association for Computing Machinery2016

Manufacturing and Tests of the European 1 MW, 170 GHz CW Gyrotron Prototype for ITER

Stefano Alberti, Jean-Philippe Hogge, Konstantinos Avramidis

An industrial 1 MW, 170 GHz continuous-wave (CW) gyrotron prototype has been manufactured in 2015 at Thales. The physical design is provided by the European GYrotron Consortium (EGYC) and is supported by the construction and the measurement of a modular sh ...

IEEE2016

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