Multiple instructions on multiple data

Applied sciences
Génie informatique
Calcul intensif
Parallélisme (informatique)

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Publications associées (29)

Transactions Chasing Scalability and Instruction Locality on Multicores

Pinar Tözün

For several decades, online transaction processing (OLTP) has been one of the main server applications that drives innovations in the data management ecosystem, and in turn the database and computer architecture communities. Recent hardware trends oblige s ...

EPFL2014

Energy-Aware Processing Platform Exploration for Embedded Biosignal Analysis

Ahmed Yasir Dogan

According to the World Health Organization, lifestyle-related diseases, e.g., cardiovascular diseases are the major cause of mortality worldwide. An accurate and continuous medical supervision is highly required for diagnosis and treatment of such diseases ...

EPFL2013

An integrated, programming model-driven framework for NoC-QoS support in cluster-based embedded many-cores

Giovanni De Micheli, Luca Benini, Federico Angiolini, Jaime Joven Murillo

Embedded SoC designs are embracing the many-core paradigm to deliver the required performance to run an ever-increasing number of applications in parallel. Networks-on-Chip (NoC) are considered as a convenient technology to implement many-core embedded pla ...

Elsevier2013

Multi-Core Architecture Design for Ultra-Low-Power Wearable Health Monitoring Systems

David Atienza Alonso, Andreas Peter Burg, Jeremy Hugues-Felix Constantin, Martino Ruggiero, Ahmed Yasir Dogan

Personal health monitoring systems can offer a cost-effective solution for human healthcare. To extend the lifetime of health monitoring systems, we propose a near-threshold ultra-low- power multi-core architecture featuring low-power cores, yet capable of ...

ACM and IEEE Press2012

OLTP on Hardware Islands

Anastasia Ailamaki, Pinar Tözün, Miguel Sérgio De Oliveira Branco, Danica Porobic, Ippokratis Pandis

Modern hardware is abundantly parallel and increasingly heterogeneous. The numerous processing cores have non-uniform access latencies to the main memory and to the processor caches, which causes variability in the communication costs. Unfortunately, datab ...

2012

Reducing OLTP Instruction Misses With Thread Migration

Anastasia Ailamaki, Pinar Tözün

During an instruction miss a processor is unable to fetch instructions. The more frequent instruction misses are the less able a modern processor is to find useful work to do and thus performance suffers. Online transaction processing (OLTP) suffers from h ...

2012

Processor Speed Control with Thermal Constraints

Giovanni De Micheli, David Atienza Alonso, Srinivasan Murali

We consider the problem of adjusting speeds of multiple computer processors, sharing the same thermal environment, such as a chip or multichip package. We assume that the speed of each processor (and associated variables such as power supply voltage) can b ...

2009

Adaptive Load Sharing for Network Processors

Jean-Yves Le Boudec

A novel scheme for processing packets in a router is presented that provides load sharing among multiple network processors distributed within the router. It is complemented by a feedback control mechanism designed to prevent processor overload. Incoming t ...

2008

Event-Based Programming without Inversion of Control

Martin Odersky, Philipp Haller

The actor computation model is especially suited for concurrent and distributed computations. Actors are basically concurrent processes which communicate through asynchronous message passing. When combined with pattern matching for messages, actor-based pr ...

2006

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