Publications associées à Bus mastering

Software Support for Non-Volatile Memory (NVM) Programming

Non-Volatile Memory (NVM) is an emerging type of memory device that provides fast, byte-addressable, and high-capacity durable storage. NVM sits on the memory bus and allows durable data structures designs similar to the in-memory equivalent ones. Expensiv ...

EPFL2021

Modeling and optimization of dedicated bus lanes space allocation in large networks with dynamic congestion

Nikolaos Geroliminis, Dimitrios Tsitsokas, Anastasios Kouvelas

Dedicated bus lanes provide a low cost and easily implementable strategy to improve transit service by minimizing congestion-related delays. Identifying the best spatial distribution of bus-only lanes in order to maximize traffic performance of an urban ne ...

2021

GPU-accelerated data management under the test of time

Anastasia Ailamaki, Syed Mohammad Aunn Raza, Periklis Chrysogelos, Angelos Christos Anadiotis, Panagiotis Sioulas

GPUs are becoming increasingly popular in large scale data center installations due to their strong, embarrassingly parallel, processing capabilities. Data management systems are riding the wave by using GPUs to accelerate query execution, mainly for analy ...

2020

Method and System for Fault Detection and Faulted Line Identification in Power Systems using Synchrophasors-Based Real-Time State Estimation

Mario Paolone, Paolo Romano, Marco Pignati, Lorenzo Zanni

A method for a faulted line identification in a power network, including, at a generic time-instant, solving a plurality of parallel phasor measurement units based real-time state estimators, the state estimators having among each other different and augme ...

2017

Optimal Software Patching Plan for PMUs

Jean-Yves Le Boudec, Ola Nils Anders Svensson, Teklemariam Tsegay Tesfay

Phasor measurement units (PMUs) deployed to monitor the state of an electrical grid need to be patched from time to time to prevent attacks that exploit vulnerabilities in the software. Applying some of these patches requires a PMU reboot, which takes the ...

2017

Architectural Support for Coherent Architecturally Visible Storage in Instruction Set Extensions

Ties Jan Henderikus Kluter

When it comes to performance, embedded systems share many problems with their higher-end counterparts. The growing gap between top processor frequency and memory access speed, the memory wall, is one such problem. Driven, in part, by low energy consumption ...

EPFL2010

An Application-Specific Design Methodology for STbus Crossbar Generation

Giovanni De Micheli, Srinivasan Murali

As the communication requirements of current and future Multiprocessor Systems on Chips (MPSoCs) continue to increase, scalable communication architectures are needed to support the heavy communication demands of the system. This is reflected in the recent ...

2005