Publications associées à Loi d'Amdahl

Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-constrained Cycles

Paolo Ienne, Kubilay Atasu, Jovan Blanusa

Cycles are one of the fundamental subgraph patterns and being able to enumerate them in graphs enables important applications in a wide variety of fields, including finance, biology, chemistry, and network science. However, to enable cycle enumeration in r ...

Assoc Computing Machinery2023

Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-Constrained Cycles

Paolo Ienne, Kubilay Atasu, Jovan Blanusa

Finding cycles in directed graphs enables important applications in various domains such as finance, biology, chemistry, and network science. However, as the size of graph datasets continues to grow, it becomes increasingly difficult to discover cycles wit ...

arXiv2023

Acceleration of graph pattern mining and applications to financial crime

Jovan Blanusa

Various forms of real-world data, such as social, financial, and biological networks, can be represented using graphs. An efficient method of analysing this type of data is to extract subgraph patterns, such as cliques, cycles, and motifs, from graphs. For ...

EPFL2023

High Performance Computing for gravitational lens modeling: Single vs double precision on GPUs and CPUs

Jean-Paul Richard Kneib, Markus Rexroth, Christoph Ernst René Schäfer

Strong gravitational lensing is a powerful probe of cosmology and the dark matter distribution. Efficient lensing software is already a necessity to fully use its potential and the performance demands will only increase with the upcoming generation of tele ...

ELSEVIER2020

Fast Energy Estimation Through Partial Execution of HPC Applications

Marina Zapater Sancho, José Luis Ayala Rodrigo

In order to optimize the energy use of servers in Data Centers, techniques such as power capping or power budgeting are usually deployed. These techniques rely on the prediction of the power and execution time of applications. These data are obtained via d ...

IEEE2018

Reducing circuit design complexity for neuromorphic machine learning systems based on Non-Volatile Memory arrays

Yusuf Leblebici, Alessandro Fumarola

Machine Learning (ML) is an attractive application of Non-Volatile Memory (NVM) arrays [1,2]. However, achieving speedup over GPUs will require minimal neuron circuit sharing and thus highly area-efficient peripheral circuitry, so that ML reads and writes ...

2017

Parallelizing Query Optimization on Shared-Nothing Architectures

Christoph Koch, Immanuel Trummer

Data processing systems offer an ever increasing degree of parallelism on the levels of cores, CPUs, and processing nodes. Query optimization must exploit high degrees of parallelism in order not to gradually become the bottleneck of query evaluation. We s ...

Assoc Computing Machinery2016

Automatic Generation of Efficient Accelerators for Reconfigurable Hardware

Christos Kozyrakis, Yunqi Zhang

Acceleration in the form of customized datapaths offer large performance and energy improvements over general purpose processors. Reconfigurable fabrics such as FPGAs are gaining popularity for use in implementing application-specific accelerators, thereby ...

Ieee2016

GPGPU-Accelerated Parallel and Fast Simulation of Thousand-core Platforms

David Atienza Alonso, Luca Benini, Martino Ruggiero, Shivani Raghav

The multicore revolution and the ever-increasing complexity of computing systems is dramatically changing system design, analysis and programming of computing platforms. Future architectures will feature hundreds to thousands of simple processors and on-ch ...

IEEE/ACM Press2011

The effects of practice schedule and critical thinking prompts on learning and transfer of a complex judgment task

Many instructional strategies that appear to improve learners' performance during training may not realize adequate posttest performance or transfer to a job. The converse has been found to be true as well: Instructional strategies that appear to slow the ...

2011

Exact quantification of the sub-optimality of uniprocessor fixed-priority pre- emptive scheduling

Thomas Rothvoss

This paper examines the relative effectiveness of fixed priority pre-emptive scheduling in a uniprocessor system, compared to an optimal algorithm. The quantitative metric used in this comparison is the processor speedup factor, equivalent to the factor by ...

2009

Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs

Paolo Ienne, Yusuf Leblebici, Philip Brisk, Alessandro Cevrero, Panagiotis Athanasopoulos, Ajay Kumar Verma, Hadi Parandeh Afshar

The Field Programmable Counter Array (FPCA) was introduced to improve FPGA performance for arithmetic circuits. An FPCA is a reconfigurable IP core that can be integrated into an FPGA. To exploit the FPCA, a circuit is transformed by merging disparate addi ...

ACM2008

A Dynamically Constrained Genetic Algorithm For Hardware-software Partitioning

Pierre-André Mudry, Guillaume Zufferey

In this article, we describe the application of an enhanced genetic algorithm to the problem of hardware-software codesign. Starting from a source code written in a high-level language our algorithm determines, using a dynamically-weighted fitness function ...

Association for Computing Machinery2006