Publications associées à Ordonnancement de travaux informatiques

From C/C plus plus Code to High-Performance Dataflow Circuits

Paolo Ienne, Andrea Guerrieri, Lana Josipovic

High-level synthesis (HLS) tools typically generate statically scheduled datapaths. Static scheduling implies that the resulting circuits have a hard time exploiting parallelism in code with potential memory dependences, with control dependences, or where ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

A dynamic scheduling tool and a methodology for creating digital twin of manufacturing systems for achieving Zero Defect Manufacturing

Foivos Psarommatis Giannakopoulos

Nowadays manufacturing environment is highly volatile and rapidly changing as the need of products is increasing exponentially, due to the fact that Product Life Cycle is shortened and therefore more products are required to be manufactured or remanufactur ...

EPFL2021

Operating System and Network Co-Design for Latency-Critical Datacenter Applications

Evangelos Marios Kogias

Datacenters are the heart of our digital lives. Online applications, such as social-networking and e-commerce, run inside datacenters under strict Service Level Objectives for their tail latency. Tight latency SLOs are necessary for such services to remain ...

EPFL2020

Thread-Placement Learning

Rachid Guerraoui, Vasileios Trigonakis, Karolos Antoniadis

In a non-uniform memory access machine, the placement of software threads to hardware cores can have a significant effect on the performance of concurrent applications. Detecting the best possible placement for each application is a necessity for thread sc ...

IEEE COMPUTER SOC2020

Stretch: Balancing QoS and Throughput for Colocated Server Workloads on SMT Cores

Boris Robert Grot, Siddharth Gupta

In a drive to maximize resource utilization, today's datacenters are moving to colocation of latency-sensitive and batch workloads on the same server. State-of-the-art deployments, such as those at Google, colocate such diverse workloads even on a single S ...

IEEE2019

QSpike tools: a generic framework for parallel batch preprocessing of extracellular neuronal signals recorded by substrate nnicroelectrode arrays

Michele Giugliano, Eleni Vasilaki

Micro-Electrode Arrays (MEAs) have emerged as a mature technique to investigate brain (dys)functions in vivo and in in vitro animal models. Often referred to as "smart" Petri dishes, MEAs have demonstrated a great potential particularly for medium-throughp ...

Frontiers Research Foundation2014

Attaining Single-Chip, High-Performance Computing Through 3D Systems with Active Cooling

David Atienza Alonso, Mohamed Mostafa Sabry Aly, Ayse Kivilcim Coskun, Jie Meng

Three-dimensional (3D) stacking is an attractive method for designing large manycore chips as it provides high transistor integration densities, improves manufacturing yield due to smaller chip area, reduces wirelength and capacitance, and enables heteroge ...

Institute of Electrical and Electronics Engineers2011

Temperature-Aware Processor Frequency Assignment for MPSoCs Using Convex Optimization

Giovanni De Micheli, David Atienza Alonso, Srinivasan Murali

The increasing processing capability of Multi-Processor Systems-on-Chips (MPSoCs) is leading to an increase in chip power dissipation, which in turn leads to significant increase in chip temperature. An important challenge facing the MPSoC designers is to ...

2007