The ever-growing global internet traffic has increased demand for higher speed data transmission. As the bandwidth requirements of wireline links increase, extensive digital equalization techniques are required to compensate for the high-frequency channel ...
This work presents an ADC-bascd receiver (RX) data-path for frame-based PAM-4 modulation with a cyclic prefix (CP). Similar to discrete multi-tone (DMT) modulation, a frame of PAM-4 symbols arc protected from the channel delay spread by the CP taps. A PAM- ...
The exponential growth of Internet traffic and related demands for higher communication speed pushes processor-to-processor and processor-to-memory interconnects to provide further higher data-rate. Often time, processor-to-memory interconnectsâ speed is ...
This paper presents a parallel implementation technique of digital equalizer for high-speed wireline serial link receiver (RX). In wireline RX, inter-symbol interference (ISI) is mitigated by continuous-time linear equalizer, and the remaining ISI is cance ...
This paper presents a wireline serial data transceiver (TRX) architecture employing a concept of single-sideband (SSB) modulation to transmit data over a multi-drop (MD) electrical link with deep notches. The proposed TRX utilizes channel notch as a filter ...
The performance of systems employing bit-interleaved coded modulation (BICM) critically depends on the availability of soft information. In the multi-antenna case, the extraction of optimum bit-metrics becomes prohibitively complex, so that suboptimal solu ...
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This work deals with coding systems based on sparse graph codes. The key issue we address is the relationship between iterative (in particular belief propagation) and maximum a posteriori decoding. We show that between the two there is a fundamental connec ...
