Publications associées à Process variation (semiconductor)

An Ultralow-Power Triaxial MEMS Accelerometer With High-Voltage Biasing and Electrostatic Mismatch Compensation

This article presents a triaxial micro electromechani-cal system (MEMS) capacitive accelerometer using a high-voltage biasing technique to achieve high resolution with ultralow power. The accelerometer system generates a differential pair of high voltages ...

Ieee-Inst Electrical Electronics Engineers Inc2024

A 500 x 500 Dual-Gate SPAD Imager With 100% Temporal Aperture and 1 ns Minimum Gate Length for FLIM and Phasor Imaging Applications

Edoardo Charbon, Claudio Bruschini, Andrei Ardelean, Paul Mos, Arin Can Ülkü, Michael Alan Wayne

In this article, we report on SwissSPAD3 (SS3), a 500 x 500 pixel single-photon avalanche diode (SPAD) array, fabricated in 0.18-mu m CMOS technology. In this sensor, we introduce a novel dual-gate architecture with two contiguous temporal windows, or gate ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

New Insights for Parasitic Effects of Label-Free Biosensors Based on Capacitive Micromachined Ultrasonic Transducers

Sandro Carrara, Zhengwen Jiang, Yihe Zhao, Jie Li

Capacitive micromachined ultrasonic transducers (CMUTs) are regarded as an attractive candidate in bio-applications such as imaging and molecule monitoring. However, the previous researches on biochemical sensing are mostly air-coupled application based on ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Production of phosphorene nanoribbons

Vasiliki Tileli

Phosphorene is a mono-elemental, two-dimensional (2D) substance with outstanding, highly directional properties and a bandgap that depends on the number of layers of the material(1-8). Nanoribbons, meanwhile, combine the flexibility and unidirectional prop ...

NATURE PUBLISHING GROUP2019

Effect of hysteretic and non-hysteretic negative capacitance on tunnel FETs DC performance

Mihai Adrian Ionescu, Igor Stolichnov, Farzan Jazaeri, Ali Saeidi

This work experimentally demonstrates that the negative capacitance effect can be used to significantly improve the key figures of merit of tunnel field effect transistor (FET) switches. In the proposed approach, a matching condition is fulfilled between a ...

2018

Robustness Analysis of Controllable-Polarity Silicon Nanowire Devices and Circuits

Hassan Ghasemzadeh Mohammadi

Substantial downscaling of the feature size in current CMOS technology has confronted digital designers with serious challenges including short channel effect and high amount of leakage power. To address these problems, emerging nano-devices, e.g., Silicon ...

EPFL2016

Analysis and Characterization of Variability in Subthreshold Source-Coupled Logic Circuits

Alexandre Schmid, Seyed Armin Tajalli, Mahsa Shoaran, Yusuf Leblebici

This article explores the effect of device parameter variations on the performance of subthreshold source-coupled logic (STSCL) circuits. A test chip has been fabricated in a standard CMOS 90 nm technology to study the matching properties of STSCL circuits ...

2015

Investigation of the dominant 1/f noise source in silicon nanowire sensors

Sara Rigante, Jan Brunner, Christian David

We analyzed 1/f noise in silicon nanowire ion-sensitive field-effect transistors (SiNW-ISFETs) having different wire widths ranging from 100 nm to 1 pin and operated under different gating conditions in order to determine the noise source and the sensor ac ...

Elsevier2014

Tri-gate silicon nanowire transistors for ultra-low pH resolution and improved scalability

Enrico Accastelli

The scalability of on-chip analytical systems based on field-effect transistors as pH sensors is limited by the degradation of the signal to noise ratio when decreasing the device size. Nano-sized tri-gate transistors such as silicon nanowires and nanoribb ...

EPFL2014

Digitization Technique for UWB Receiver and Capacitive Sensor Interface

Shenjie Wang

As CMOS processes continue to scale to smaller dimensions, the increased fT of the devices and smaller parasitic capacitance allow formore power efficient and faster digital circuits to be made. But at the same time, output impedance of transistors has gon ...

EPFL2014

An Accelerated Stress Test Method for Electrostatically Driven MEMS Devices

Jinyu Jason Ruan

This paper addresses an innovative solution to develop a circuit to perform accelerated stress tests of capacitive microelectromechanical-system (MEMS) switches and shows the use of instruments and equipment to monitor physical aging phenomena. A dedicated ...

Institute of Electrical and Electronics Engineers2012

Process Variation and Leakage Power

Bahman Kheradmand Boroujeni

Technology scaling improves the energy, performance, and area of the digital circuits. With further scaling into sub-45nm regime, we are moving toward very low supply (VDD) and threshold voltages (VT), smaller VDD/VT ratio, high leakage current, and large ...

EPFL2011

Design Tradeoffs in Ultra-Low-Power Digital Nano-Scale CMOS

Seyed Armin Tajalli, Yusuf Leblebici

In ultra-low-power (ULP) applications, the supply voltage is generally reduced well below threshold voltage of MOS devices in order to limit dissipation and to control the device leakage current due to the subthreshold channel residual current. However, re ...

Institute of Electrical and Electronics Engineers2011